參數(shù)資料
型號(hào)： FT232HQ-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù)： 10/65頁(yè)
文件大?。?/td> 0K
描述： IC HS USB TO UART/FIFO 48QFN
應(yīng)用說明： FT1248 Application Note
標(biāo)準(zhǔn)包裝： 1
通道數(shù)： 1，UART
FIFO's： 4kb
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 1.98 V，2.97 V ~ 3.63 V
帶并行端口： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN（8x8）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 768-1102-6
Copyright 2012 Future Technology Devices International Limited
18
Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
3.5.5 FT232H pins used in an MPSSE
The FT232H has a Multi-Protocol Synchronous Serial Engine (MPSSE). This mode is enabled by sending a
software command (FT_SetBitMode) to the FTDI D2xx driver. The MPSSE can be configured to a number
of industry standard serial interface protocols such as JTAG, I2C or SPI (MASTER), or it can be used to
implement a proprietary bus protocol. For example, it is possible to connect FT232H’s to an SRAM
configurable FPGA such as supplied by Altera or Xilinx. The FPGA device would normally not be configured
(i.e. have no defined function) at power-up. Application software on the PC could use the MPSSE (and
D2XX driver) to download configuration data to the FPGA over USB. This data would define the hardware
function on power up. The MPSSE can be used to control a number of GPIO pins. When configured in this
mode, the pins used and the descriptions of the signals are shown in Table 3.10
Pin No.
Name
Type
MPSSE Configuration Description
13
TCK/SK
OUTPUT
Clock Signal Output. For example:
JTAG – TCK, Test interface clock
SPI (MASTER) – SK, Serial Clock
14
TDI/DO
OUTPUT
Serial Data Output. For example:
JTAG – TDI, Test Data Input
SPI (MASTER) – DO
15
TDO/DI
INPUT
Serial Data Input. For example:
JTAG – TDO, Test Data output
SPI (MASTER) – DI, Serial Data Input
16
TMS/CS
OUTPUT
Output Signal Select. For example:
JTAG – TMS, Test Mode Select
SPI (MASTER) – CS, Serial Chip Select
17
GPIOL0
I/O
General Purpose input/output
18
GPIOL1
I/O
General Purpose input/output
19
GPIOL2
I/O
General Purpose input/output
20
GPIOL3
I/O
General Purpose input/output
21
GPIOH0
I/O
General Purpose input/output
25
GPIOH1
I/O
General Purpose input/output
26
GPIOH2
I/O
General Purpose input/output
27
GPIOH3
I/O
General Purpose input/output
28
GPIOH4
I/O
General Purpose input/output
29
GPIOH5
I/O
General Purpose input/output
30
GPIOH6
I/O
General Purpose input/output
31
GPIOH7
I/O
General Purpose input/output
Table 3.10 MPSSE Configured Pin Descriptions
For functional description of this mode, please refer to section 4.8
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