參數(shù)資料
型號(hào)： FT232HQ-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù)： 30/65頁(yè)
文件大?。?/td> 0K
描述： IC HS USB TO UART/FIFO 48QFN
應(yīng)用說(shuō)明： FT1248 Application Note
標(biāo)準(zhǔn)包裝： 1
通道數(shù)： 1，UART
FIFO's： 4kb
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 1.98 V，2.97 V ~ 3.63 V
帶并行端口： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN（8x8）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 768-1102-6
Copyright 2012 Future Technology Devices International Limited
36
Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
4.8 MPSSE Interface Mode Description.
MPSSE Mode is designed to allow the FT232H to interface efficiently with synchronous serial protocols
such as JTAG, I2C and SPI (MASTER) Bus. It can also be used to program SRAM based FPGA’s over USB.
The MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous
serial protocol (industry standard or proprietary) to be implemented using the FT232H.
MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can
be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of
30 Mbits/s.
When the FT232H is configured in MPSSE mode, the IO timing and signals used are shown in
Figure 4.14 and Table 4.4 These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to
be provide a slower clock.
Figure 4.14 MPSSE Signal Waveforms
Name
Min
Typ
Max
Units
Comments
t1
16.67
15.15
ns
CLKOUT period
t2
7.5
8.33
9.17
ns
CLKOUT high period
t3
7.5
8.33
9.17
ns
CLKOUT low period
t4
1
7.15
ns
CLKOUT to TDI/DO delay
t5
0
ns
TDI/DO hold time
t6
11
ns
TDI/DO setup time
Table 4.4 MPSSE Signal Timings
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