參數(shù)資料
型號(hào)： FPD85310VJD
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Panel Timing Controller
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 9/29頁(yè)
文件大?。?/td> 440K
代理商： FPD85310VJD
Functional Description
(Continued)
TABLE 1. Input Mode Definition
INPUT FORMAT
FIXED VERTICAL,
FIXED HORIZONTAL
determined by the INPUT
CONTROL REGISTER bits [1:0]
FIXED VERTICAL,
FIXED HORIZONTAL
(FIX VERTICAL = 1,
FIX HORIZONTAL = 1)
FIXED VERTICAL,
ENAB HORIZONTAL
(FIXED VERTICAL = 1,
FIXED HORIZONTAL = 0)
ENAB ONLY
(FIXED VERTICAL = 0,
FIXED HORIZONTAL = 0)
HORIZONTAL
DATA START
VERTICAL
DATA START
Programmable from HSYNC Falling Edge
(# INPUT CLKS)
Programmable from VSYNC
Falling Edge
(# HSYNC PERIODS)
Data Valid during ENAB high (HSYNC is
IGNORED)
Programmable from VSYNC
Falling Fdge
(# HSYNC PERIODS)
Data Valid during ENAB High (HSYNC is
IGNORED)
First ENAB after ENAB low for
greater than one line time (VSYNC
is IGNORED)
Note:
INPUT CONTROL REGISTER bit[2] “Enab Detection” provides for “auto-detection” of ENAB. When “1” and Enab is not toggling, the controller will automatically
set the input mode to Fixed Vertical, Fixed Horizontal.
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