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參數(shù)資料
| 型號： | FPD85310VJD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Panel Timing Controller |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 12/29頁 |
| 文件大?。?/td> | 440K |
| 代理商： | FPD85310VJD |
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Functional Description
(Continued)
TABLE 2. FPD85310 Programmable Register Definition
(Continued)
Control
Registers
EEPROM
Address
The control registers provide mode setting information to the input and output interfaces.
[3]
Enable/Disable Virtual 8-bit (8-bit input only)
“0” = Virtual 8-bit enabled
“1” = Virtual 8-bit disabled (Truncate LSBs)
Eight/Six Bit Video
“0” = Six Bit Video
“1” = Eight Bit Video
Power-up Delay (TEST2 must be “0”)
“00” = Outputs active after second VSYNC
“01” = Outputs active after third VSYNC
“10” = Outputs active after fourth VSYNC
“11” = Outputs active after fifth VSYNC
White Data Generation
“0” = No white data generation
“1” = Enables white data generation during vertical blanking
# of HSYNCS from VSYNC falling edge until start of video
[4]
[6:5]
[7]
Vertical
Backporch (11
bits)
Horizontal
Backporch (11
bits)
General
Purpose Output
Registers
(9 sets)
DA, D9
D8, D7
# of 65 MHz clocks after the falling edge of HSYNC until start of video
See
Table 3
EEPROM
Memory
Map
The GPO registers provide complete control over placement of control edges/strobes within the
data frame. The GPO timing registers (Vertical Start, Vertical Duration, Horizontal Start, and
Horizontal Duration) define the control timing relative to the internal line and pixel counters. The
line counter corresponds to the line being displayed. The pixel counter corresponds to the pixel
output each line. The Control Register provides polarity selection and/or generation of a line to
line frame-to-frame alternating signal (REV). Each General Purpose Output can be uniquely
configured. See the GPO programming examples for details.
- GPO [0] provides for the data inversion function enabled by bit 3 of the Output Format Control
Register
- GPO [8] provides programmable data and clock blanking
Line # at which GPO [X] control generation begins
Vertical Start
(11 bits)
Vertical
Duration
(11 bits)
Horizontal Start
(10 bits)
# lines GPO [X] control generation continues
(if “0”, Vertical component is always on)
Internal count (pixel counter) at which GPO [X] goes active to be triggered on rising edge of the
OCLK
Note: If control register [1] = “1”, start position will be moved by 1 pixel clock
# Pixel Clocks/2 GPO [X] is active after Horizontal Start
(if “0”, Horizontal component is always on)
Horizontal
Duration
(11 bits)
www.national.com
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| FPD87208 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs |
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| FPD87310VHB | 功能描述:IC CTRLR PANEL TIMING 80-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| FPD87346 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
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