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參數(shù)資料
| 型號： | FPD85310VJD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Panel Timing Controller |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 440K |
| 代理商： | FPD85310VJD |
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APPENDIX A: GPO Programming
Examples
(Continued)
GPO Programming Example #2:
Generate a control signal which transitions low 20 output
clocks after the beginning of each output line, has a pulse-
width (low) of 12 μs, and goes high during horizontal blank-
ing. This control signal is used as an output enable for the
gate drivers.
Horizontal time (clocks/line) = 1300 dot clocks
Vertical period (lines/frame) = 850 lines
Control is active beginning at line 2 and remains active for
768 lines.
GPO Vertical Start Register = 2
GPO Vertical Duration Register = 768d (300h)
Negative pulse goes low each line at output clock 20 corre-
sponding to when the 39/40 pixels are output on OR, OG,
OB, ER, EG, EB. Pulse remains low for 390 output clocks
(390 x 30.8 ns/clock = 12 μs). (Dual Bus output clock =
32.5 MHz for 65 MHz XGA video, 1024 pixels/line, 768 lines/
frame).
Note:
6 counts are added to the output clock # because the GPO start count
begins 6 clocks prior to the output data.
GPO Horizontal Start Register = 26d (1ah)
GPO Horizontal Duration Register = 390d (186h)
The control pulses are negative (bit [0] = 1) and the toggle
circuitry is disabled (bit1 [1] = 0).
GPO Control Register = 1
DS101086-24
www.national.com
26
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| FPD87310VHB | 功能描述:IC CTRLR PANEL TIMING 80-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| FPD87346 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
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