參數(shù)資料
型號: FPD85310VJD
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: Panel Timing Controller
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數(shù): 25/29頁
文件大?。?/td> 440K
代理商: FPD85310VJD
APPENDIX A: GPO Programming Examples
(Continued)
GPO Programming Example #1:
Generate a control signal which transitions high at the end of
each line, has a pulsewidth of 3 μs, and remains low during
the vertical blanking period. This control is used for the latch
pulse to the column drivers.
Horizontal time (clocks/line) = 1300 dot clocks
Vertical period (lines/frame) = 850 lines
Vertical control is active beginning at line 1 and remains ac-
tive for 768 lines.
GPO Vertical Start Register = 1
GPO Vertical Duration Register = 768d (300h)
Positive pulse goes high each line at output clock 512 corre-
sponding to when the last two pixels are output on OR, OG,
OB, ER, EG, EB. Pulse remains high for 98 output clocks (98
x 30.8 ns/clock = 3.02 μs). (Dual Bus output clock =
32.5 MHz for 65 MHz XGA video, 1024 pixels/line, 768 dis-
played lines/frame).
Note:
6 counts are added to the output start # because the GPO pixel count
begins 6 clocks prior to the output data.
GPO Horizontal Start Register = 518d (206h)
GPO Horizontal Duration Register = 98d (62h)
The control pulses are positive (bit [0] = 0) and the toggle cir-
cuitry is disabled (bit1 [1] = 0).
GPO Control Register = 0
DS101086-23
www.national.com
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