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參數(shù)資料
| 型號： | flas00xx |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard(多媒體卡) |
| 中文描述： | 多媒體卡（多媒體卡） |
| 文件頁數(shù)： | 66/79頁 |
| 文件大?。?/td> | 516K |
| 代理商： | FLAS00XX |
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MultiMediaCard Flash
Preliminary MultiMediaCard Product Manual;
1998 SANDISK CORPORATION
Page 66 of 79
All previous examples dealt with the scenario of the host stopping the data transmission
during an active data transfer. The following two diagrams describe a scenario of receiving
the stop transmission between data blocks. In the first example the card is busy
programming the last block while in the second the card is idle. However, there are still un-
programmed data blocks in the input buffers. These blocks are being programmed as soon
as the stop transmission command is received and the card activates the busy signal.
Figure 5-17 Stop Transmission Received After Last Data Block. Card is Busy Programming
.
Figure 5-18 Stop Transmission Received After Last Data Block. Card Becomes Busy
.
Stream Write
—The data transfer starts N
WR
clock cycles after the card response to the
sequential write command was received. The bus transaction is identical to that of a write
block command (see Figure 5-13). As the data transfer is not block oriented, the data
stream does not include the CRC checksum. Consequently the host can not receive any
CRC status information from the card. The data stream is terminated by a stop command.
The bus transaction is identical to the write block option when a data block is interrupted
by the stop command (see Figure 5-15).
Erase, Set and Clear Write Protect Timing
—The host must first tag the sectors to erase
using the tag commands (CMD32 - CMD37). The erase command (CMD38), once issued,
will erase all tagged sectors. Similarly, set and clear write protect commands start a
programming operation as well. The card will signal “busy” (by pulling the DAT line low) for
the duration of the erase or programming operation. The bus transaction timings are
described in Figure 5-18.
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