參數(shù)資料
型號： flas00xx
廠商： SIEMENS AG
英文描述： MultiMediaCard(多媒體卡)
中文描述： 多媒體卡（多媒體卡）
文件頁數(shù)： 63/79頁
文件大?。?/td> 516K
代理商： FLAS00XX
MultiMediaCard Flash
Preliminary MultiMediaCard Product Manual;
1998 SANDISK CORPORATION
Page 63 of 79
<---- Host Command ---->
<-N
ID
Cycles->
<---- CID or OCR --->
CMD S
T
Content
CRC
E
Z
* * * * * *
Z
S
T
Content
Z
Z
Z
Figure 5-7 Identification Timing (Card Identification Mode)
Last Card Response - Next Host Command Timing
—After receiving the last card
response, the host can start the next command transmission after at least N
RC
clock cycles.
This timing is relevant for any host command.
<-------- Response -------->
<-N
RC
Cycles ->
<---- Host Command ----->
CMD
S
T
Content
CRC
E
Z
* * * * * *
Z
S
T
Content
CRC
E
Figure 5-8 Timing Response End to Next CMD Start (Data Transfer Mode)
Last Host Command - Next Host Command Timing Diagram—After the last command has
been sent, the host can continue sending the next command after at least N
CC
clock
periods.
<----- Host Command ---->
<-N
CC
Cycles ->
<---- Host Command ----->
CMD
S
T
Content
CRC
E
Z
* * * * * *
Z
S
T
Content
CRC
E
Figure 5-9 Timing CMD n End to CMD n+1 Start (All Modes)
In the case the CMD
n
command was a last acquisition command no more responded by
any card, than the next CMD
n+1
command is allowed to follow after at least N
CC
+136 (the
length of the R2 response) clock periods.
5.10.2 Data Read
Single Block Read—The host selects one card for data read operation by CMD7, and sets
the valid block length for block oriented data transfer by CMD16. The basic bus timing for
a read operation is given in Figure 5-10. The sequence starts with a single block read
command (CMD17) which specifies the start address in the argument field. The response
is sent on the CMD line as usual.
<----- Host Command ----->
<-N
CR
Cycles ->
<-------- Response --------->
CMD
S
T
Content
CRC
E
Z Z
P
* * *
P
S
T
Content
CRC
E
<-------- N
AC
Cycles ------->
<- Read Data
DAT
Z
Z
Z
* * * *
Z
Z
Z
Z
Z
Z
P
* * * * * * * * * *
P
S
D D
D * * *
Figure 5-10 Transfer of Single Block Read
Data transmission from the card starts after the access time delay NAC beginning from the
end bit of the read command. After the last data bit, the CRC check bits are suffixed to
allow the host to check for transmission errors.
Multiple Block Read
—In multiple block read mode, the card sends a continuous flow of
data blocks following the initial host read command. The data flow is terminated by a stop
transmission command (CMD12). Figure 5-11 describes the timing of the data blocks and
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