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參數(shù)資料
| 型號(hào)： | flas00xx |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard(多媒體卡) |
| 中文描述： | 多媒體卡（多媒體卡） |
| 文件頁(yè)數(shù)： | 62/79頁(yè) |
| 文件大?。?/td> | 516K |
| 代理商： | FLAS00XX |
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MultiMediaCard Flash
Preliminary MultiMediaCard Product Manual;
1998 SANDISK CORPORATION
Page 62 of 79
5.10 Timings
All timing diagrams use the following schematics and abbreviations:
Table 5-26 Timing Diagram Symbols
S
Start Bit (= 0)
T
Transmitter Bit (Host = 1, Card = 0)
P
One-cycle Pull-up (= 1)
E
End Bit (=1)
Z
High Impedance State (-> = 1)
D
Data Bits
*
Repeater
CRC
Cyclic Redundancy Check Bits (7 Bits)
Card Active
Host Active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the
card respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the
pull-up resistors R
CMD
respectively R
DAT
. Actively-driven P-bits are less sensitive to noise
superposition.
All timing values are defined in Table 5-27.
5.10.1 Command and Response
Both host command and card response are clocked out with the rising edge of the host
clock. The minimum delay between the host command and card response is N
CR
clock
cycles. This timing diagram is relevant for host command CMD3.
<---- Host Command ---->
<-NCR Cycles->
<-------- Response --------->
CMD S
T
Content
CRC
E
Z
* * * * * *
Z
S
T
Content
CRC
E
Z
Z
Z
Figure 5-5 Command Response Timing (Identification Mode)
There is a two Z bit period followed by P bits pushed up by the responding card. This
timing diagram is relevant for all responded host commands except CMD1,2,3.
<---- Host Command
----> <-N
CR
Cycles->
<-------- Response --------->
CMD S
T
Content
CRC
E
Z
Z
P
* * *
P
S
T
Content
CRC
E
Z
Z
Z
Figure 5-6 Command Response Timing (Data Transfer Mode)
Card Identification and Card Operation Conditions Timing
—The card identification
(CMD2) and card operation conditions (CMD1) timing are processed in the open-drain
mode. The card response to the host command starts after exactly N
ID
clock cycles.
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