參數(shù)資料
型號(hào)： flas00xx
廠(chǎng)商： SIEMENS AG
英文描述： MultiMediaCard(多媒體卡)
中文描述： 多媒體卡（多媒體卡）
文件頁(yè)數(shù)： 13/79頁(yè)
文件大小： 516K
代理商： FLAS00XX
MultiMediaCard Flash
Preliminary MultiMediaCard Product Manual;
1998 SANDISK CORPORATION
Page 13 of 79
In this mode there is no validity check on the transferred data.
The start address for a read operation can be any random byte address in the valid
address space of n the memory card. For a write operation, the start address must be
sector aligned and the data length must be an integer multiplication of the sector length.
Single Block Mode
In this mode the host reads or writes one data block in a pre-specified length. The data
block transmission is protected with 16 bit CRC which is generated by the sending unit and
checked by the receiving unit.
The block length, for read operations, is limited by the device sector size but can be as
small as a single byte. Misalignment is not allowed. Every data block must be contained in
a single memory sector.
The block length for write operations must be identical to the sector size and the start
address aligned to a sector boundary.
Multiple Block Mode
This mode is similar to the single block mode, but the host can read/write multiple data
blocks (all have the same length) which will be stored or retrieved from contiguous
memory addresses starting at the address specified in the command.
The operation is terminated with a stop transmission command.
Misalignment and block length restrictions apply to multiple blocks as well and are identical
to the single block read/write operations.
1.5.8.7 Data Transfer Rate
The average data transfer rate for the MultiMediaCard is 1 Mbyte/sec for read and 200
Kbyte/Sec for write (erase time is included) at 3.3 Volts. Therefore the maximum clock
frequency for stream read/write mode (where contiguous data stream is either sent to or,
expected from, the card) is 8MHz
and 600KHz
for read and write respectively.
In block mode, where time gaps can be inserted between data blocks, the maximum clock
frequency is 20MHz. The typical access time (latency) for each data block, in read
operation, is 1.5ms
.
The write block operation is done in handshake mode. The card will
keep data line DAT low as long as the write operation is in progress and there are no write
buffers available.
1.5.8.8 Data Protection in the Flash Card
Every sector is protected with an Error Correction Code (ECC). The ECC is generated (in
the memory card) when the sectors are written and validated when the data is read. If
defects are found, the data is corrected prior to transmission to the host.
The MultiMediaCard can be considered error free and no additional data protection is
needed. However, if an application uses additional, external, ECC protection, the data
organization is defined in the user writeable section of the CSD register.
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