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參數(shù)資料
| 型號(hào)： | FDW2520C |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Thermoelectric Cooler Controller |
| 中文描述： | 熱電冷卻器控制器 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 416K |
| 代理商： | FDW2520C |
REV. C
ADN8830
–19–
Power Supply Ripple
Minimizing ripple on the power supply voltage can be an impor-
tant consideration, particularly in signal source laser applications.
If the laser diode is operated from the same supply rail as the TEC
controller, ripple on the supply voltage could cause inadvertent
modulation of the laser frequency. As most laser diodes are driven
from a 5 V supply, it is recommended the ADN8830 be operated
from a separate 3.3 V regulated supply unless higher TEC voltages
are required. Operation from 3.3 V also improves efficiency, thus
minimizing power dissipation.
The power supply ripple is primarily a function of the supply by-
pass capacitance, also called bulk capacitance, and the inductor
ripple current. Similar to the L-C filter at the PWM amplifier
output, using more capacitance with low equivalent series resis-
tance (ESR) will lower the supply ripple. A larger inductor value
will reduce the inductor ripple current, but this may not be
practical in the application. A recommended approach is to use a
standard electrolytic capacitor in parallel with a low ESR capacitor.
A surface-mount 220
μ
F electrolytic in parallel with a 22
μ
F poly-
mer aluminum low ESR capacitor can occupy an approximate total
board area of only 0.94 square inches or 61 square millimeters.
Using these capacitors along with a 4.7
μ
H inductor can yield a
supply ripple of less than 5 mV.
High frequency transient spikes may appear on the supply voltage
as well. This is due to the fast switching times on the PWM transis-
tors and the sharp edges of their gate voltages. Although these
transient spikes can reach several tens of millivolts at their peak,
they typically last for less than 20 ns and have a resonance greater
than 100 MHz. Additional bulk capacitance will not appreciably
affect the level of these spikes as such capacitance is not reactive at
these frequencies. Adding 0.01
μ
F ceramic capacitors on the sup-
ply line near the PWM PMOS transistor can reduce this switching
noise. Inserting an RF inductor with a High-Q around 100 MHz in
series with PVDD will also block this noise from traveling back to
the power supply.
Setting Maximum Output Current and Short-Circuit
Protection
Although the maximum output voltage can be programmed
through VLIM to protect the TEC from overvoltage damage,
the user may wish to protect the ADN8830 circuit from a possible
short circuit at the output. Such a short could quickly damage the
external FETs or even the power supply since they would attempt
to drive excessive current. Figure 20 shows a simple modification
that will protect the system from an output short circuit.
SD
C1
1 F
R2
1k
DENOTES
PGND
R1
1M
D1
MA116CT-ND
OR
EQUIVALENT
AVDD
Q1
FDV304P
OR EQUIVALENT
PVDD
R
S
10m
R4
100k
R3
1k
PVDD
DENOTES
AGND
TO
FETS
AND
DECOUPLING
CAPS
V
S
V
X
AD8601
Figure 20. Implementing Output Short-Circuit Protection
A 10 m
resistor placed in series with the PVDD supply line creates a
voltage drop proportional to the absolute value of the output current.
The AD8601 is a CMOS amplifier that is configured as a com-
parator. As long as the voltage at its inverting input (V
S
) exceeds
the voltage set by the resistor divider at the noninverting input (V
X
),
the gate of Q1 will remain at ground. This leaves Q1 on, effectively
connecting D1 to the positive rail and leaving the voltage on C1 at
V
DD
. Should enough current flow through R
S
to drop V
S
below V
X
,
Q1 will turn off and C1 will discharge through R2 down to a logic
low to activate the ADN8830 shutdown. Once V
S
returns to a
voltage greater than V
X
, Q1 will turn back on and C1 will charge
back to V
DD
through R1. The shutdown and reactivation time
constants are approximately
C
R
C
R
=
×
1
1
The shutdown time constant should be a minimum of 10 clock
cycles to ensure high current switching transients do not trigger a
false activation. If powered from 5 V, the circuit shown will shut
down the ADN8830 should PVDD deliver over 5 A for more than
1 ms. After shutdown, the circuit will reactivate the ADN8830 in
about 1 second.
The voltage drop across
R
S
is found as
SD
ON
=
×
1
1
(42)
V
I
R R
V
DD
η
R
OUT
S
S
=
2
(43)
where
R
L
is the load resistance or resistance of the TEC and is
the efficiency of the system. An estimate of efficiency can be calculated
either from the Calculating Power Dissipation and Efficiency section
or from Figures 16 and 17. A reasonable approximation is =
0.85. Although the exact resistance of a TEC varies with tempera-
ture, an estimation can be made by dividing the maximum voltage
rating of the TEC by its maximum current rating.
In addition to providing protection against a short at the output,
this circuit will also protect the FETs against shoot-through current.
Shoot-through will not occur when using the recommended
transistors and additional capacitance shown in Tables V and VI.
However, if different transistors are used where their shoot-
through potential is unknown, implementing the short-circuit
protection circuit will unconditionally protect these transistors.
To set a maximum output current limit, use the circuit in Figure
21. This circuit can share the 10 m
power supply shunt resistor
as the short-circuit protection circuit to sense the output current.
In normal operation Q1 is on, pulling the ADN8830 VLIM pin
down to the voltage set by VLIMIT. This sets the maximum out-
put voltage limit as described in the Setting the Maximum TEC
Voltage and Current section.
TO
VLIM
R2
1.47k
DENOTES
PGND
AVDD
Q1
FDV301N
OR
EQUIVALENT
PVDD
R
S
10m
R4
100k
R3
178
PVDD
DENOTES
AGND
V
SY
V
X
AD8605
VLIMIT
(0V TO 1.5V)
R1
3.48k
C1
1nF
TO
FETS
AND
DECOUPLING
CAPS
Figure 21. Setting a Maximum Output Current Limit
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