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參數(shù)資料
| 型號： | FDM2452NZ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 小信號晶體管 |
| 英文描述： | CAP CER 2.2UF 50V Y5V 1206 |
| 中文描述： | 8100 mA, 30 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封裝： | 2 X 5 MM, MLP-6 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 137K |
| 代理商： | FDM2452NZ |
FDM2452NZ Rev C1
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage,
V
GS
= 0 V,
I
D
= 250
μ
A
30
V
BV
DSS
T
J
I
DSS
I
GSS
On Characteristics
V
GS(th)
V
GS(th)
T
J
R
DS(on)
I
D
= 250
μ
A, Referenced to 25
°
C
24
mV/
°
C
V
DS
= 24 V,
V
GS
=
±
12 V,
V
GS
= 0 V
V
DS
= 0 V
1
μ
A
μ
A
±
10
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
,
I
D
= 250
μ
A, Referenced to 25 C
V
GS
= 4.5 V,
I
D
= 8.1 A
V
GS
= 4.0 V,
I
D
= 8.0 A
V
GS
= 3.1 V,
I
D
= 7.7 A
V
GS
= 2.5 V,
I
D
= 7.4 A
V
GS
= 4.5 V, I
D
= 8.1 A, T
J
=125
°
C
V
DS
= 5 V,
I
D
=8.1 A
I
D
= 250
μ
A
0.55
0.8
–3
1.5
V
mV/
°
C
13.6
13.9
14.6
15.7
19
46
21
21.5
23
25
31
m
g
FS
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
R
G
Gate Resistance
Forward Transconductance
S
980
160
110
1.8
pF
pF
pF
V
DS
= 15 V,
f = 1.0 MHz
V
GS
= 0 V,
V
GS
= 0 V,
f = 1.0 MHz
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
9
10
30
8.7
14
1.8
3.8
18
20
48
17
19
ns
ns
ns
ns
nC
nC
nC
V
DD
= 15 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 15 V,
V
GS
= 4.5 V
I
D
= 8.1 A,
Drain–Source Diode Characteristics
V
SD
Drain–Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery Time
Q
rr
Diode Reverse Recovery Charge
V
GS
= 0 V,
I
S
= 1.8 A
(Note 2)
0.7
1.2
V
15
4
nS
nC
I
F
= 8.1 A,
dI
F
/dt = 100 A/μs
Notes:
1.
R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a)
55°C/W when
mounted on a 1in
2
pad
of 2 oz copper
b) 145°C/W when mounted on a
minimum pad of 2 oz copper
Scale 1 : 1 on letter size paper
2
.
Pulse Test: Pulse Width < 300
μ
s,
Duty Cycle < 2.0%
3. The diode connected between the gate
and source serves only as protection
againts ESD. No gate overvoltage
rating is implied.
F
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