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| 型號： | EVAL-ADF4351EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD 1 EVAL FOR ADF4351 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ADF4351
Data Sheet
Rev. 0 | Page 12 of 28
MUXOUT AND LOCK DETECT
The multiplexer output on the ADF4351 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by the M3, M2, and M1 bits in Register 2 (see Figure 26).
Figure 19 shows the MUXOUT section in block diagram form.
DGND
DVDD
CONTROL
MUX
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N DIVIDER OUTPUT
DGND
RESERVED
THREE-STATE OUTPUT
DVDD
09800-
008
Figure 19. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4351 digital section includes a 10-bit RF R counter,
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. As shown in Figure 2, the control bits are the three LSBs:
DB2, DB1, and DB0. Table 6 shows the truth table for these bits.
Figure 23 summarizes how the latches are programmed.
Table 6. Truth Table for the C3, C2, and C1 Control Bits
Control Bits
Register
C3
C2
C1
0
Register 0 (R0)
0
1
Register 1 (R1)
0
1
0
Register 2 (R2)
0
1
Register 3 (R3)
1
0
Register 4 (R4)
1
0
1
Register 5 (R5)
PROGRAM MODES
modes are set up in the ADF4351.
The following settings in the ADF4351 are double buffered: phase
value, modulus value, reference doubler, reference divide-by-2,
R counter value, and charge pump current setting. Before the part
uses a new value for any double-buffered setting, the following
two events must occur:
1. The new value is latched into the device by writing to the
appropriate register.
2. A new write is performed on Register 0 (R0).
For example, any time that the modulus value is updated,
Register 0 (R0) must be written to, to ensure that the modulus
value is loaded correctly. The divider select value in Register 4
(R4) is also double buffered, but only if the DB13 bit of
Register 2 (R2) is set to 1.
VCO
The VCO core in the ADF4351 consists of three separate VCOs,
each of which uses 16 overlapping bands, as shown in Figure 20,
to allow a wide frequency range to be covered without a large
VCO sensitivity (KV) and resultant poor phase noise and spur-
ious performance.
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
V
T
UNE
(V)
FREQUENCY (GHz)
09800-
120
Figure 20. VTUNE vs. Frequency
The correct VCO and band are selected automatically by the
VCO and band select logic at power-up or whenever Register 0
(R0) is updated.
VCO and band selection take 10 PFD cycles multiplied by the
value of the band select clock divider. The VCO VTUNE is discon-
nected from the output of the loop filter and is connected to an
internal reference voltage.
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