- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16549 > EVAL-ADF4351EB1Z (Analog Devices Inc)BOARD 1 EVAL FOR ADF4351 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADF4351EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD 1 EVAL FOR ADF4351 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
ADF4351
Data Sheet
Rev. 0 | Page 20 of 28
Charge Cancelation
Setting the DB21 bit to 1 enables charge pump charge cancel-
ation. This has the effect of reducing PFD spurs in integer-N
mode. In fractional-N mode, this bit should be set to 0.
CSR Enable
Setting the DB18 bit to 1 enables cycle slip reduction. CSR is
a method for improving lock times. Note that the signal at the
phase frequency detector (PFD) must have a 50% duty cycle for
cycle slip reduction to work. The charge pump current setting
must also be set to a minimum. For more information, see the
Clock Divider Mode
Bits[DB16:DB15] must be set to 10 to activate phase resync
(see the Phase Resync section). These bits must be set to 01
to activate fast lock (see the Fast Lock Timer and Register
Sequences section). Setting Bits[DB16:DB15] to 00 disables
the clock divider (see Figure 27).
12-Bit Clock Divider Value
Bits[DB14:DB3] set the 12-bit clock divider value. This value
is the timeout counter for activation of phase resync (see the
Phase Resync section). The clock divider value also sets the
timeout counter for fast lock (see the Fast Lock Timer and
Register Sequences section).
REGISTER 4
Control Bits
When Bits[C3:C1] are set to 100, Register 4 is programmed.
Figure 28 shows the input data format for programming this
register.
Feedback Select
The DB23 bit selects the feedback from the VCO output to the
N counter. When this bit is set to 1, the signal is taken directly
from the VCO. When this bit is set to 0, the signal is taken from
the output of the output dividers. The dividers enable coverage
of the wide frequency band (34.375 MHz to 4.4 GHz). When
the dividers are enabled and the feedback signal is taken from
the output, the RF output signals of two separately configured
PLLs are in phase. This is useful in some applications where the
positive interference of signals is required to increase the power.
RF Divider Select
Bits[DB22:DB20] select the value of the RF output divider (see
Band Select Clock Divider Value
Bits[DB19:DB12] set a divider for the band select logic clock input.
By default, the output of the R counter is the value used to clock
the band select logic, but, if this value is too high (>125 kHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Figure 28).
VCO Power-Down
Setting the DB11 bit to 0 powers the VCO up; setting this bit to 1
powers the VCO down.
Mute Till Lock Detect (MTLD)
When the DB10 bit is set to 1, the supply current to the RF output
stage is shut down until the part achieves lock, as measured by
the digital lock detect circuitry.
AUX Output Select
The DB9 bit sets the auxiliary RF output. If DB9 is set to 0, the
auxiliary RF output is the output of the RF dividers; if DB9 is set
to 1, the auxiliary RF output is the fundamental VCO frequency.
AUX Output Enable
The DB8 bit enables or disables the auxiliary RF output. If DB8
is set to 0, the auxiliary RF output is disabled; if DB8 is set to 1,
the auxiliary RF output is enabled.
AUX Output Power
Bits[DB7:DB6] set the value of the auxiliary RF output power
level (see Figure 28).
RF Output Enable
The DB5 bit enables or disables the primary RF output. If DB5
is set to 0, the primary RF output is disabled; if DB5 is set to 1,
the primary RF output is enabled.
Output Power
Bits[DB4:DB3] set the value of the primary RF output power
level (see Figure 28).
REGISTER 5
Control Bits
When Bits[C3:C1] are set to 101, Register 5 is programmed.
Figure 29 shows the input data format for programming this
register.
Lock Detect Pin Operation
Bits[DB23:DB22] set the operation of the lock detect (LD) pin
(see Figure 29).
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the ADF4351 registers should be started in the
following sequence:
1. Register 5
2. Register 4
3. Register 3
4. Register 2
5. Register 1
6. Register 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GEM25DRYF | CONN EDGECARD 50POS DIP .156 SLD |
| GEM28DRTF | CONN EDGECARD 56POS DIP .156 SLD |
| H3AWH-4006G | IDC CABLE - HSC40H/AE40G/HPL40H |
| GEM28DRKF | CONN EDGECARD 56POS DIP .156 SLD |
| M1CXA-5036J | IDC CABLE - MKC50A/MC50G/X |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4360-0EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| EVAL-ADF4360-1EB1 | 制造商:Analog Devices 功能描述:Evaluation Board For ADF4360-1 |
| EVAL-ADF4360-1EBZ1 | 功能描述:BOARD EVALUATION FOR ADF4360-1 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| EVAL-ADF4360-2EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADF4360-2 |
| EVAL-ADF4360-2EBZ1 | 功能描述:BOARD EVALUATION FOR ADF4360-2 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。