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| 型號： | EVAL-ADF4351EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD 1 EVAL FOR ADF4351 |
| 標準包裝： | 1 |
| 系列： | * |
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ADF4351
Data Sheet
Rev. 0 | Page 4 of 28
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Minimum RF Output Power3
4
dBm
Programmable in 3 dB steps
Maximum RF Output Power3
5
dBm
Output Power Variation
±1
dB
Minimum VCO Tuning Voltage
0.5
V
Maximum VCO Tuning Voltage
2.5
V
NOISE CHARACTERISTICS
VCO Phase Noise Performance
VCO noise is measured in open-loop conditions
89
dBc/Hz
10 kHz offset from 2.2 GHz carrier
114
dBc/Hz
100 kHz offset from 2.2 GHz carrier
134
dBc/Hz
1 MHz offset from 2.2 GHz carrier
148
dBc/Hz
5 MHz offset from 2.2 GHz carrier
86
dBc/Hz
10 kHz offset from 3.3 GHz carrier
111
dBc/Hz
100 kHz offset from 3.3 GHz carrier
134
dBc/Hz
1 MHz offset from 3.3 GHz carrier
145
dBc/Hz
5 MHz offset from 3.3 GHz carrier
83
dBc/Hz
10 kHz offset from 4.4 GHz carrier
110
dBc/Hz
100 kHz offset from 4.4 GHz carrier
131
dBc/Hz
1 MHz offset from 4.4 GHz carrier
145
dBc/Hz
5 MHz offset from 4.4 GHz carrier
Normalized Phase Noise Floor
(PN
SYNTH)
PLL loop BW = 500 kHz
220
dBc/Hz
ABP = 6 ns
221
dBc/Hz
ABP = 3 ns
Normalized 1/f Noise (PN
1_f)
10 kHz offset; normalized to 1 GHz
116
dBc/Hz
ABP = 6 ns
118
dBc/Hz
ABP = 3 ns
In-Band Phase Noise
100
dBc/Hz
3 kHz from 2111.28 MHz carrier
Integrated RMS Jitter6
0.27
ps
Spurious Signals Due to PFD
Frequency
80
dBc
Level of Signal with RF Mute Enabled
40
dBm
1 I
CP is internally modified to maintain constant loop gain over the frequency range.
2 T
A = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz.
3 Using 50 resistors to V
VCO, into a 50 load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the
main output.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log fPFD. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: PNSYNTH = PNTOT 10 log(fPFD) 20 log N.
5 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f
RF)
and at a frequency offset (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 f
REFIN = 122.88 MHz; fPFD = 30.72 MHz; VCO frequency = 4222.56 MHz; RFOUT = 2111.28 MHz; N = 137; loop BW = 60 kHz; ICP = 2.5 mA; low noise mode. The noise was
measured with an EVAL-ADF4351EB1Z and the Rohde & Schwarz FSUP signal source analyzer.
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