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| 型號： | EVAL-ADF4351EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD 1 EVAL FOR ADF4351 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ADF4351
Data Sheet
Rev. 0 | Page 24 of 28
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantiza-
tion noise of the Σ-Δ modulator also depends on the particular
phase word with which the modulator is seeded.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
lookup table of phase values corresponding to each frequency
can be created for use when programming the ADF4351.
If a lookup table is not used, keep the phase word at a constant
value to ensure consistent spur levels on any particular frequency.
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of the
MOD phase offsets with respect to the input reference, where
MOD is the fractional modulus. The phase resync feature of
the ADF4351 produces a consistent output phase offset with
respect to the input reference. This phase offset is necessary in
applications where the output phase and frequency are important,
such as digital beamforming. See the Phase Programmability
section to program a specific RF output phase when using
phase resync.
Phase resync is enabled by setting Bits[DB16:DB15] in
Register 3 to 10. When phase resync is enabled, an internal
timer generates sync signals at intervals of tSYNC given by the
following formula:
tSYNC = CLK_DIV_VALUE × MOD × tPFD
where:
CLK_DIV_VALUE is the decimal value programmed in
Bits[DB14:DB3] of Register 3. This value can be any integer
from 1 to 4095.
MOD is the modulus value programmed in Bits[DB14:DB3]
of Register 1 (R1).
tPFD is the PFD reference period.
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The tSYNC time must be programmed to
a value that is at least as long as the worst-case lock time. This
guarantees that the phase resync occurs after the last cycle slip
in the PLL settling transient.
In the example shown in Figure 33, the PFD reference is 25 MHz
and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to
400 s by programming CLK_DIV_VALUE = 80.
LE
PHASE
FREQUENCY
SYNC
(INTERNAL)
–100
0
100
200
1000
300
400
500
600
700
800
900
TIME (s)
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
tSYNC
LAST CYCLE SLIP
PLL SETTLES TO
INCORRECT PHASE
09800-
020
Figure 33. Phase Resync Example
Phase Programmability
The phase word in Register 1 controls the RF output phase. As
this word is swept from 0 to MOD, the RF output phase sweeps
over a 360° range in steps of 360°/MOD. In many applications,
it is advisable to disable VCO band selection by setting Bit DB28
in Register 1 (R1) to 1. This setting selects the phase adjust feature.
High PFD Frequencies
VCO band selection is required to ensure that the correct VCO
band is chosen for the relevant frequency. VCO band selection
can operate with PFD frequencies up to 45 MHz using the high
VCO band select mode (set Bit DB23 in Register 3 to 1).
For PFD frequencies higher than 45 MHz, it is recommended
that the user perform the following steps:
1. Program the desired VCO frequency with phase adjustment
disabled (set Bit DB28 in Register 1 to 0). Ensure that the
PFD frequency is less than 45 MHz.
2. After the correct frequency is achieved, enable phase adjust-
ment (set Bit DB28 in Register 1 to 1).
3. PFD frequencies higher than 32 MHz are permissible only
with integer-N applications; therefore, set the antibacklash
pulse width to 3 ns (set Bit DB22 in Register 3 to 1).
4. Using the desired PFD frequency, program the appropriate
values for the reference R and feedback N counters.
Using this procedure, the lowest rms in-band phase noise can
be achieved.
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