Limit at TMIN, T
參數(shù)資料
型號: EVAL-AD2S1210EDZ
廠商: Analog Devices Inc
文件頁數(shù): 34/36頁
文件大小: 0K
描述: BOARD EVAL AD2S1210
標準包裝: 1
主要目的: 接口,旋轉(zhuǎn)變壓至數(shù)字
嵌入式:
已用 IC / 零件: AD2S1210
主要屬性: 10 ~ 16 位分辨率,3125 rps 最大(10 位)或 1024 脈沖
次要屬性: 圖形用戶界面
已供物品: 板,CD
產(chǎn)品目錄頁面: 788 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD2S1210CSTZ-ND - IC CONV R/D VAR RES OSC 48-LQFP
AD2S1210BSTZ-ND - IC CONV R/D 10-16BIT 48-LQFP
AD2S1210ASTZ-ND - IC CONV R/D 10-16BIT 48-LQFP
AD2S1210
Rev. A | Page 7 of 36
Parameter
Description
Limit at TMIN, TMAX
Unit
t29
Delay WR/FSYNC rising edge to SDO high-Z
15
ns min
t30
Delay from SAMPLE before WR/FSYNC falling edge
6 × tCK + 20 ns
ns min
t31
Delay CS falling edge to WR/FSYNC falling edge in normal mode
2
ns min
t32
A0 and A1 setup time before WR/FSYNC falling edge
2
ns min
t33
A0 and A1 hold time after WR/FSYNC falling edge2
In normal mode, A0 = 0, A1 = 0/1
24 × tCK + 5 ns
ns min
In configuration mode, A0 = 1, A1 = 1
8 × tCK + 5 ns
ns min
t34
Delay WR/FSYNC rising edge to WR/FSYNC falling edge
10
ns min
fSCLK
Frequency of SCLK input
VDRIVE = 4.5 V to 5.25 V
20
MHz
VDRIVE = 2.7 V to 3.6 V
25
MHz
VDRIVE = 2.3 V to 2.7 V
15
MHz
1 Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
2 A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.
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