AVDD = DVDD" />
參數(shù)資料
型號(hào)： EVAL-AD2S1210EDZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/36頁
文件大?。?/td> 0K
描述： BOARD EVAL AD2S1210
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，旋轉(zhuǎn)變壓至數(shù)字
嵌入式： 否
已用 IC / 零件： AD2S1210
主要屬性： 10 ~ 16 位分辨率，3125 rps 最大（10 位）或 1024 脈沖
次要屬性： 圖形用戶界面
已供物品： 板，CD
產(chǎn)品目錄頁面： 788 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD2S1210CSTZ-ND - IC CONV R/D VAR RES OSC 48-LQFP
AD2S1210BSTZ-ND - IC CONV R/D 10-16BIT 48-LQFP
AD2S1210ASTZ-ND - IC CONV R/D 10-16BIT 48-LQFP
AD2S1210
Rev. A | Page 6 of 36
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
Description
Limit at TMIN, TMAX
Unit
fCLKIN
Frequency of clock input
6.144
MHz min
10.24
MHz max
tCK
Clock period ( = 1/fCLKIN)
98
ns min
163
ns max
t1
A0 and A1 setup time before RD/CS low
2
ns min
t2
Delay CS falling edge to WR/FSYNC rising edge
22
ns min
t3
Address/data setup time during a write cycle
3
ns min
t4
Address/data hold time during a write cycle
2
ns min
t5
Delay WR/FSYNC rising edge to CS rising edge
2
ns min
t6
Delay CS rising edge to CS falling edge
10
ns min
t7
Delay between writing address and writing data
2 × tCK + 20
ns min
t8
A0 and A1 hold time after WR/FSYNC rising edge
2
ns min
t9
Delay between successive write cycles
6 × tCK + 20
ns min
t10
Delay between rising edge of WR/FSYNC and falling edge of RD
2
ns min
t11
Delay CS falling edge to RD falling edge
2
ns min
t12
Enable delay RD low to data valid in configuration mode
VDRIVE = 4.5 V to 5.25 V
37
ns min
VDRIVE = 2.7 V to 3.6 V
25
ns min
VDRIVE = 2.3 V to 2.7 V
30
ns min
t13
RD rising edge to CS rising edge
2
ns min
t14A
Disable delay RD high to data high-Z
16
ns min
t14B
Disable delay CS high to data high-Z
16
ns min
t15
Delay between rising edge of RD and falling edge of WR/FSYNC
2
ns min
t16
SAMPLE pulse width
2 × tCK + 20
ns min
t17
Delay from SAMPLE before RD/CS low
6 × tCK + 20
ns min
t18
Hold time RD before RD low
2
ns min
t19
Enable delay RD/CS low to data valid
VDRIVE = 4.5 V to 5.25 V
17
ns min
VDRIVE = 2.7 V to 3.6 V
21
ns min
VDRIVE = 2.3 V to 2.7 V
33
ns min
t20
RD pulse width
6
ns min
t21
A0 and A1 set time to data valid when RD/CS low
VDRIVE = 4.5 V to 5.25 V
36
ns min
VDRIVE = 2.7 V to 3.6 V
37
ns min
VDRIVE = 2.3 V to 2.7 V
29
ns min
t22
Delay WR/FSYNC falling edge to SCLK rising edge
3
ns min
t23
Delay WR/FSYNC falling edge to SDO release from high-Z
VDRIVE = 4.5 V to 5.25 V
16
ns min
VDRIVE = 2.7 V to 3.6 V
26
ns min
VDRIVE = 2.3 V to 2.7 V
29
ns min
t24
Delay SCLK rising edge to DBx valid
VDRIVE = 4.5 V to 5.25 V
24
ns min
VDRIVE = 2.7 V to 3.6 V
18
ns min
VDRIVE = 2.3 V to 2.7 V
32
ns min
t25
SCLK high time
0.4 × tSCLK
ns min
t26
SCLK low time
0.4 × tSCLK
ns min
t27
SDI setup time prior to SCLK falling edge
3
ns min
t28
SDI hold time after SCLK falling edge
2
ns min
相關(guān)PDF資料
PDF描述
MAX6162AESA+T IC VREF SERIES PREC 2.048V 8SOIC
207W234-3-0 BOOT MOLDED
RP40-2412DGW/N-HC CONV DC/DC 40W 9-36VIN +/-12VOUT
V110B5C100BL2 CONVERTER MOD DC/DC 5V 100W
ADR370ARTZ-REEL7 IC VREF SERIES PREC SOT-23-3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD4001FMCZ 功能描述:EVAL BOARD FOR AD4001 制造商:analog devices inc. 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):16 采樣率（每秒）:2M 數(shù)據(jù)接口:SPI，DSP 輸入范圍:±VREF 不同條件下的功率（典型值）:20mW @ 2MSPS 使用的 IC/零件:AD4001 所含物品:板，電源 標(biāo)準(zhǔn)包裝:1
EVAL-AD421EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Loop-Powered 4 mA to 20 mA DAC
EVAL-AD5025EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
EVAL-AD5045EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
EVAL-AD5060EB 制造商:Analog Devices 功能描述:EVAL BD FOR AD506X DAC 14-/16BIT, SERL INPUT - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*