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| 型號： | EVAL-AD2S1210EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD2S1210 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，旋轉(zhuǎn)變壓至數(shù)字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1210 |
| 主要屬性： | 10 ~ 16 位分辨率，3125 rps 最大（10 位）或 1024 脈沖 |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板，CD |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD2S1210CSTZ-ND - IC CONV R/D VAR RES OSC 48-LQFP AD2S1210BSTZ-ND - IC CONV R/D 10-16BIT 48-LQFP AD2S1210ASTZ-ND - IC CONV R/D 10-16BIT 48-LQFP |
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AD2S1210
Rev. A | Page 18 of 36
Table 6. Fault Detection Decoding
Condition
DOS Pin
LOT Pin
Order of
Priority
Loss of Signal (LOS)
0
1
Degradation of Signal (DOS)
0
1
2
Loss of Tracking (LOT)
1
0
3
No Fault
1
N/A
Sine/Cosine Input Clipping
The AD2S1210 indicates that a clipping error has occurred if
any of the resolver input pins (SIN, SINLO, COS, or COSLO)
are clipping the power rail or ground rail of the AD2S1210. The
clipping fault is indicated if the input amplitudes are less than
0.15 V or greater then AVDD 0.2 V for more than 4 μs.
Sine/cosine input clipping error is indicated by both the DOS and
LOT pins latching as logic low outputs. Sine/cosine input clipping
error is also indicated by Bit D7 of the fault register being set high.
The DOS and LOT pins are reset to a no fault state when the
user enters configuration mode and reads the fault register.
Configuration Parity Error
The AD2S1210 includes a number of user programmable registers
that allow the user to configure the part. Each read/write register
on the AD2S1210 is programmed with seven bits of informa-
tion by the user. The 8th bit is reserved as a parity error bit. In
the event that the data within these registers becomes corrupted,
the AD2S1210 indicates that a configuration parity error has
occurred. Configuration parity error is indicated by both the DOS
and LOT pins latching as logic low outputs. Configuration parity
error is also indicated by Bit D0 of the fault register being set
high. In the event that a parity error occurs, it is recommended
that the user reset the part using the RESET pin.
Phase Lock Error
The AD2S1210 indicates that a phase lock error has occurred if
the difference between the phase of the excitation frequency
and the phase of the sine and cosine signals exceeds the specified
phase lock range. Phase lock error is indicated by a logic low on
the LOT pin and is not latched. Phase lock error is also indicated
by Bit D1 of the fault register being set high.
ON-BOARD PROGRAMMABLE SINUSOIDAL
OSCILLATOR
An on-board oscillator provides the sinusoidal excitation signal
(EXC) to the resolver as well as its complemented signal (EXC).
The frequency of this reference signal is programmable to a
number of standard frequencies between 2 kHz and 20 kHz.
The amplitude of this signal is 3.6 V p-p and is centered on 2.5 V.
The reference excitation output of the AD2S1210 needs an
external buffer amplifier to provide gain and the additional
current to drive a resolver.
The AD2S1210 also provides an internal synthetic reference
signal that is phase locked to its sine and cosine inputs. Phase
errors between the resolver primary and secondary windings
can degrade the accuracy of the RDC and are compensated by
this synchronous reference signal. This also compensates the
phase shifts due to temperature and cabling and eliminates the
need of an external preset phase compensation circuit.
SYNTHETIC REFERENCE GENERATION
When a resolver undergoes a high rotation rate, the RDC tends
to act as an electric motor and produces speed voltages, along
with the ideal sine and cosine outputs. These speed voltages are
in quadrature to the main signal waveform. Moreover, nonzero
resistance in the resolver windings causes a nonzero phase shift
between the reference input and the sine and cosine outputs.
The combination of speed voltages and phase shift causes a track-
ing error in the RDC that is approximated by
Frequency
Reference
Rate
Rotation
Shift
Phase
Error
×
=
(6)
To compensate for the described phase error between the resolver
reference excitation and the sine/cosine signals, an internal
synthetic reference signal is generated in phase with the refer-
ence frequency carrier. The synthetic reference is derived using
the internally filtered sine and cosine signals. It is generated
by determining the zero crossing of either the sine or cosine
(whichever signal is larger, to improve phase accuracy) and
evaluating the phase of the resolver reference excitation. The
synthetic reference reduces the phase shift between the refer-
ence and sine/cosine inputs to less than 10°, and operates for
phase shifts of ±44°. If additional phase lock range is required,
Bit D5 in the control register can be set to zero to expand the
phase lock range to 360° (see the Control Register section).
CONNECTING THE CONVERTER
Ground is connected to the AGND and DGND pins (see
connected to the AVDD and DVDD pins, with typical values for the
decoupling capacitors being 10 nF and 4.7 μF. These capacitors
are then placed as close to the device pins as possible and are
connected to both AVDD and DVDD. The VDRIVE pin is connected
to the supply voltage of the microprocessor. The voltage applied
to the VDRIVE input controls the voltage of the parallel and serial
interfaces. VDRIVE can be set to 5 V, 3 V, or 2.5 V. Typical values
for the VDRIVE decoupling capacitors are 10 nF and 4.7 μF.
Typical values for the oscillator decoupling capacitors are 20 pF,
whereas typical values for the reference decoupling capacitors are
10 nF and 10 μF.
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