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參數(shù)資料
| 型號： | EVAL-AD2S1210EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD2S1210 |
| 標準包裝： | 1 |
| 主要目的： | 接口，旋轉(zhuǎn)變壓至數(shù)字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1210 |
| 主要屬性： | 10 ~ 16 位分辨率，3125 rps 最大（10 位）或 1024 脈沖 |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板，CD |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD2S1210CSTZ-ND - IC CONV R/D VAR RES OSC 48-LQFP AD2S1210BSTZ-ND - IC CONV R/D 10-16BIT 48-LQFP AD2S1210ASTZ-ND - IC CONV R/D 10-16BIT 48-LQFP |
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AD2S1210
Rev. A | Page 19 of 36
48 47
RE
F
O
UT
46
RE
F
BY
P
45
CO
S
44
CO
S
L
O
43
AV
DD
42
SI
N
L
O
41
SI
N
40
AG
ND
39
EX
C
38
EX
C
37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
CLKIN
6
DVDD
5
DGND
1
8
XTALOUT
9
10
12
11
13 14 15 16 17 18
V
DRI
V
E
19
DG
ND
20 21 22 23 24
AD2S1210
07
46
7-
02
5
20pF
8.192
MHZ
4.7F
10nF
5V
10nF
10F
4.7F
10nF
BUFFER
CIRCUIT
BUFFER
CIRCUIT
S2
R2
S4
S3
S1
R1
10nF
VDRIVE
4.7F
Figure 27 shows a suggested buffer circuit. Capacitor C1 may be
used in parallel with Resistor R2 to filter out any noise that may
exist on the EXC and EXC outputs. Care should be taken when
selecting the cutoff frequency of this filter to ensure that phase
shifts of the carrier caused by the filter do not exceed the phase
lock range of the AD2S1210.
The gain of the circuit is
))
1
/(
1
(
)
/
(
ω
C1
R2
R1
R2
Gain
Carrier
×
+
×
=
(7)
and
IN
REF
OUT
V
C1
R2
R1
R2
R1
R2
V
×
+
×
+
×
=
ω
1
(8)
where:
ω is the radian frequency of the applied signal.
VREF, a dc voltage, is set so that VOUT is always a positive value,
eliminating the need for a negative supply.
C1
R2
R1
12V
5V
EXC/EXC
(VIN)
(VREF)
VOUT
07
46
7-
02
6
AD8662
Figure 26. Connecting the AD2S1210 to a Resolver
In this recommended configuration, the converter introduces a
VREF/2 offset in the SIN, SINLO, COS, and COSLO signal outputs
from the resolver. The sine and cosine signals can each be
connected to a different potential relative to ground if the sine
and cosine signals adhere to the recommended specifications.
Note that because the EXC and EXC outputs are differential,
there is an inherent gain of 2×.
Figure 27. Buffer Circuit
A separate screened twisted pair cable is recommended for the
analog input pins, SIN, SINLO, COS, and COSLO. The screens
should terminate to either REFOUT or AGND.
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