參數(shù)資料
型號(hào): EFM32G842F128
廠商: Energy Micro
文件頁(yè)數(shù): 136/136頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,LCD,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1028-6
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
99
www.energymicro.com
Table 4.16. VTOR bit assignments
Bits
Name
Function
[31:30]
-
Reserved (in some devices these bits are part of the TBLOFF bitfield as explained below).
[29(31):7] TBLOFF
Vector table base offset field. It contains bits[29:7] (bits[31:7] for Cortex-M3 revision r2p1 and
later) of the offset of the table base from the bottom of the memory map. Table 1.1 (p. 5) shows
the Cortex-M3 revision number for the EFM32 device series.
Note
Bit[29] (bit 31 in Cortex-M3 revision r2p1 and later) determines whether the vector table
is in the code or SRAM memory region:
0 = code
1 = SRAM.
Bit[29(31)] is sometimes called the TBLBASE bit.
[6:0]
-
Reserved.
When setting TBLOFF, you must align the offset to the number of exception entries in the vector table.
The recommended alignment is 64 words, which covers all EFM32 interrupts and the 16 internal Cortex-
M3 exceptions. If you require 16 interrupts or less, the alignment can be set to 32 words.
Note
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
4.3.6 Application Interrupt and Reset Control Register
The AIRCR provides priority grouping control for the exception model, endian status for data accesses,
and reset control of the system. See the register summary in Table 4.12 (p. 94) and Table 4.17 (p.
99) for its attributes.
To write to this register, you must write 0x5VA to the VECTKEY field, otherwise the processor ignores
the write.
The bit assignments are:
On read: VECTKEYSTAT
On writ e: VECTKEY
31
16 15 14
11 10
8 7
3 2 1 0
Reserved
ENDIANESS
PRIGROUP
SYSRESETREQ
VECTCLRACTIVE
VECTRESET
Reserved for Debug use
Table 4.17. AIRCR bit assignments
Bits
Name
Type
Function
[31:16]
Write: VECTKEYSTAT
Read: VECTKEY
RW
Register key:
Reads as 0x05FA
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
[15]
ENDIANESS
RO
Always read as 0 (Little-endian)
[14:11]
-
Reserved
[10:8]
PRIGROUP
R/W
Interrupt priority grouping field. This field determines the split of group
priority from subpriority, see Section 4.3.6.1 (p. 100) .
[7:3]
-
Reserved.
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