參數(shù)資料
型號(hào): EDS5104ABTA-6B
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: RP15 (F) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; 2:1 Wide Input Voltage Range; 15 Watts Output Power; 1.6kVDC Isolation; UL Certified; Fixed Operating Frequency; Six-Sided Continuous Shield; Standard 50.8 x25.4x10.2mm Package; Efficiency to 88%
中文描述: 128M X 4 SYNCHRONOUS DRAM, 5 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁(yè)數(shù): 24/52頁(yè)
文件大小: 564K
代理商: EDS5104ABTA-6B
EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Preliminary Data Sheet E0250E10 (Ver. 1.0)
24
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11, A12: (OPCODE): The SDRAM has two types of write modes. One is the burst write
mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
A2 A1
A0
Burst length
BT=0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
4
8
R
R
1
1
1
BT=1
1
1
0
R
F.P.
1
2
4
8
R
R
R
R
A3
0 Sequential
1
Interleave
Burst type
A6
0
0
0
0
1
A5
0
0
1
1
X
A4 CAS latency
0
1
0
1
X
R
R
2
3
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
1
1
R
Write mode
Burst read and burst write
A8
0
1
0
1
Burst read and single write
R
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
X
X
X
A11
0
X
X
X
0
A12
BA0
BA1
BA1 BA0
0
X
X
X
0
X
X
X
A12
0
X
X
X
Mode Register Set Timing
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