參數(shù)資料
型號: EDS5104ABTA-6B
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: RP15 (F) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; 2:1 Wide Input Voltage Range; 15 Watts Output Power; 1.6kVDC Isolation; UL Certified; Fixed Operating Frequency; Six-Sided Continuous Shield; Standard 50.8 x25.4x10.2mm Package; Efficiency to 88%
中文描述: 128M X 4 SYNCHRONOUS DRAM, 5 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數(shù): 20/52頁
文件大?。?/td> 564K
代理商: EDS5104ABTA-6B
EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Preliminary Data Sheet E0250E10 (Ver. 1.0)
20
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
4
L
L
H
H
BA, RA
ACT
Bank and row active*
9
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh*
9
Remark: H: VIH. L: VIL.
×
: VIH or VIL
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.
L
L
L
L
MODE
MRS
Mode register set*
8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDS5104ABTA-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM
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EDS5108ABTA-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits SDRAM