參數(shù)資料
型號(hào): EDL1216CASA-10-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits Mobile RAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: LEAD FREE, FBGA-54
文件頁數(shù): 31/59頁
文件大?。?/td> 479K
代理商: EDL1216CASA-10-E
EDL1216AASA
Data Sheet E0196E30 (Ver. 3.0)
31
Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command. When the precharge
command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated
again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
READ
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
Q1
DQ
Command
Q2
Q3
Q4
ACT
t
RP
PRE
Hi-Z
(t
RAS
must be satisfied)
Precharge Termination in READ Cycle (CL = 2)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
READ
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
Q1
Q2
Q3
ACT
t
RP
PRE
Hi-Z
T8
Q4
(t
RAS
must be satisfied)
Precharge Termination in READ Cycle (CL = 3)
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