參數(shù)資料
型號(hào): EDL5132CBMA
廠商: Elpida Memory, Inc.
英文描述: 512M bits Mobile RAM MCP 2 pcs of 256Mb components (16M words x 32 bits)
中文描述: 512M位移動(dòng)內(nèi)存MCP的2 256Mb的組成部分(1,600字× 32位片)
文件頁(yè)數(shù): 1/62頁(yè)
文件大?。?/td> 570K
代理商: EDL5132CBMA
Document No. E0490E30 (Ver. 3.0)
Date Published September 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
PRELIMINARY DATA SHEET
512M bits Mobile RAM MCP
2 pcs of 256Mb components
EDL5132CBMA (16M words
×
32 bits)
Description
The EDL5132CBMA is a 512M bits Mobile RAM MCP
(Multi Chip Package) organized as 4,194,304 words
×
32 bits
×
4 banks, 2 pieces of 256M bits Mobile RAM in
one package. It is packaged in 90-ball FBGA.
Features
Low voltage power supply
VDD:
1.7V to 1.95V
VDDQ: 1.7V to 1.95V
Wide temperature range (
25
°
C to 85
°
C)
Programmable Partial Array Self Refresh
Programmable Driver Strength
Auto Temperature Compensated Self Refresh by
built-in temperature sensor.
Deep power down mode
Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every
cycle
Quad internal banks controlled by BA0 and BA1
Byte control by DQM
Wrap sequence = Sequential/ Interleave
/CAS latency (CL) = 2, 3
Automatic precharge and controlled precharge
Auto refresh and self refresh
×
32 organization
8,192 refresh cycles/64ms
Burst termination by Burst stop command and
Precharge command
FBGA package with lead free solder (Sn-Ag-Cu)
Pin Configurations
/xxx indicates active low signal.
DQ26
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
A12
A9
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
/RAS
(Top view)
DQM1
NC
NC
/CAS
/WE DQM0
VDDQ DQ8
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
DQ13 DQ15 VSS
VDD
DQ0
DQ2
90-ball FBGA
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
A0 to A12
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
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