參數(shù)資料
型號(hào): EDL1216CASA-10-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits Mobile RAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: LEAD FREE, FBGA-54
文件頁(yè)數(shù): 29/59頁(yè)
文件大?。?/td> 479K
代理商: EDL1216CASA-10-E
EDL1216AASA
Data Sheet E0196E30 (Ver. 3.0)
29
Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle
minimum. There is a restriction to avoid data conflict. The Data bus must be High-Z using DQM before WRITE.
D1
D2
D3
D4
READ
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
WRITE
DQM
Hi-Z
1cycle
Read to Write Command Interval 1
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 8
T9
Q1
Q2
Q3
READ
DQ
Command
D1
D2
D3
WRITE
DQM
Hi-Z is
necessary
Q1
Q2
READ
DQ
Command
D1
D2
D3
WRITE
DQM
Hi-Z is
necessary
/CAS latency = 2
/CAS latency = 3
Read to Write Command Interval 2
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