參數(shù)資料
型號(hào): EDL1216AASA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: GT 5C 5#16S PIN RECP WALL RM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
封裝: FBGA-54
文件頁(yè)數(shù): 1/59頁(yè)
文件大?。?/td> 479K
代理商: EDL1216AASA-75-E
Document No. E0196E30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
DATA SHEET
128M bits Mobile RAM
EDL1216AASA (8M words
×
16 bits)
Description
The EDL1216AA is a 128M bits Mobile RAM organized
as 2,097,152 words
×
16 bits
×
4 banks. The Mobile
RAM achieved low power consumption and high-speed
data transfer using the pipeline architecture. All inputs
and outputs are synchronized with the positive edge of
the clock.
This product is packaged in 54-ball FBGA (
μ
BGA
).
Features
Low voltage power supply
VDD:
2.5V
±
0.2V
VDDQ: 1.8V
±
0.15V
Wide temperature range (
25
°
C to 85
°
C)
Programmable partial self refresh
Programmable driver strength
Programmable temperature compensated self refresh
(Option)
Deep power down mode
Small package (54-ball FBGA (
μ
BGA))
Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every
cycle
Quad internal banks controlled by BA0 and BA1
Byte control by LDQM and UDQM
Wrap sequence = Sequential/ Interleave
/CAS latency (CL) = 2, 3
Automatic precharge and controlled precharge
Auto refresh and self refresh
×
16 organization
4,096 refresh cycles/64ms
Burst termination by Burst stop command and
Precharge command
FBGA(
μ
BGA) package is lead free solder (Sn-Ag-Cu)
Applications
Mobile cellular handsets, PDAs, wireless PDAs,
handheld PCs, home electronic appliances, and
information appliances, etc.
Pin Configurations
/xxx indicates active low signal.
VSS
1
A
B
C
D
E
F
G
H
J
2
3
4
5
6
7
8
9
DQ14
DQ12
DQ10
DQ8
UDQM
NC
A8
VSS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
BA1
A1
A2
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
/CS
/RAS
/CAS
/WE
UDQM
LDQM
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select
Data inputs/ outputs
Clock input
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
Upper DQ mask enable
Lower DQ mask enable
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
54-ball FBGA ( BGA)
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