參數(shù)資料
型號: EDL1216AASA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: GT 5C 5#16S PIN RECP WALL RM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
封裝: FBGA-54
文件頁數(shù): 30/59頁
文件大?。?/td> 479K
代理商: EDL1216AASA-75-E
EDL1216AASA
Data Sheet E0196E30 (Ver. 3.0)
30
Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
Burst Termination in READ Cycle
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
READ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X
Q1
Q2
Q3
DQ
/CAS latency = 2
Hi-Z
Q1
Q2
Q3
DQ
/CAS latency = 3
Hi-Z
BST
Burst Termination in READ Cycle
Remark: BST: Burst stop command
Burst Termination in WRITE Cycle
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
D2
D3
D4
WRITE
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X
BST
Hi-Z
D1
Burst Termination in WRITE Cycle
Remark: BST: Burst stop command
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