參數(shù)資料
型號(hào)： EDL1216AASA-75-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： GT 5C 5#16S PIN RECP WALL RM
中文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
封裝： FBGA-54
文件頁(yè)數(shù)： 27/59頁(yè)
文件大?。?/td> 479K
代理商： EDL1216AASA-75-E
EDL1216AASA
Data Sheet E0196E30 (Ver. 3.0)
27
Read / Write Command Interval
Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ. The interval between the
commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.
QB1
QB2
QB3
QB4
Hi-Z
READ A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
READ B
QA1
1cycle
T9
Read to Read Command Interval
Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the
commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction.
DB1
DB2
DB3
DB4
Hi-Z
WRITE A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
WRITE B
DA1
1cycle
Write to Write Command Interval
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