參數(shù)資料
型號(hào)： EDI9LC644V
英文描述： 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動(dòng)態(tài)RAM陣列)
中文描述： 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動(dòng)態(tài)內(nèi)存陣列）
文件頁(yè)數(shù)： 3/26頁(yè)
文件大小： 460K
代理商： EDI9LC644V
11
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
Write with
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Auto Precharge
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
ILLEGAL
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
No Operation; Bank(s) idle after tRP
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Precharging
L
H
L
BA
Column
Write w/o Precharge
ILLEGAL
2
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
20
L
H
L
X
Burst Termination
No Operation; Bank(s) idle after tRP
L
H
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Row Activating
L
H
L
BA
Column
Write
ILLEGAL
2
L
H
L
H
BA
Column
Read
ILLEGAL
2
L
H
L
X
Burst Termination
No Operation; Row active after tRCD
L
H
X
No Operation
No Operation; Row active after tRCD
H
X
Device Deselect
No Operation; Row active after tRCD
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Write Recovering
L
H
L
BA
Column
Write
Start Write; Determine if Auto Precharge
6
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
6
L
H
L
X
Burst Termination
No Operation; Row active after tDPL
L
H
X
No Operation
No Operation; Row active after tDPL
H
X
Device Deselect
No Operation; Row active after tDPL
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
Write Recovering
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
with Auto
L
H
L
BA
Column
Write
ILLEGAL
2,6
Precharge
L
H
L
H
BA
Column
Read
ILLEGAL
2,6
L
H
L
X
Burst Termination
No Operation; Precharge after tDPL
L
H
X
No Operation
No Operation; Precharge after tDPL
H
X
Device Deselect
No Operation; Precharge after tDPL
SDRAM CURRENT STATE TRUTH TABLE (cont.)
Current State
Command
Action
Notes
SDCE
SDRAS
SDCAS
SDWE
(BA)
SDA10-A0
Description
A11
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參數(shù)描述
EDI9LC644V1310BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM
EDI9LC644V1312BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM
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EDI9LC644V1610BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM
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