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參數(shù)資料
| 型號(hào)： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動(dòng)態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動(dòng)態(tài)內(nèi)存陣列） |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 460K |
| 代理商： | EDI9LC644V |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @
BURST LENGTH = FULL PAGE
CAb
CAa
RAa
DQ
Precharge
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Row Active
(A-Bank)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DON'T CARE
RAa
DAa0
DAa1
DAa2
DAa3
DAa4
DAb1
DAb0
DAb3
DAb2
DAb5
DAb4
Note 2
tRDL
tBDL
SDRAS
SDCAS
ADDR
A11 (BA)
BWE
SDA10
SDCLK
SDCE
SDWE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL.
BWE at write interrupt by precharge command is needed to prevent invalid write.
BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
3. Burst stop is valid at every burst length.
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相關(guān)代理商/技術(shù)參數(shù) |
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| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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