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參數(shù)資料
| 型號： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動態(tài)內(nèi)存陣列） |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 460K |
| 代理商： | EDI9LC644V |
10
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
L
OP Code
Mode Register Set
Set the Mode Register
1
L
H
X
Auto or Self Refresh
Start Auto
1
L
H
L
X
Precharge
No Operation
L
H
BA
Row Address
Bank Activate
Activate the specified bank and row
Idle
L
H
L
BA
Column
Write w/o Precharge
ILLEGAL
2
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
1
L
H
L
X
Burst Termination
No Operation
1
L
H
X
No Operation
H
X
Device Deselect
No Operation
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
3
L
H
BA
Row Address
Bank Activate
ILLEGAL
1
Row Active
L
H
L
BA
Column
Write
Start Write; Determine if Auto Precharge
4,5
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
4,5
L
H
L
X
Burst Termination
No Operation
L
H
X
No Operation
H
X
Device Deselect
No Operation
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
Terminate Burst; Start the Precharge
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Read
L
H
L
BA
Column
Write
Terminate Burst; Start the Write cycle
5,6
L
H
L
H
BA
Column
Read
Terminate Burst; Start a new Read cycle
5,6
L
H
L
X
Burst Termination
Terminate the Burst
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
Terminate Burst; Start the Precharge
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Write
L
H
L
BA
Column
Write
Terminate Burst; Start a new Write cycle
5,6
L
H
L
H
BA
Column
Read
Terminate Burst; Start the Read cycle
5,6
L
H
L
X
Burst Termination
Terminate the Burst
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
2
Read with
L
H
BA
Row Address
Bank Activate
ILLEGAL
2
Auto Precharge
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
ILLEGAL
L
H
X
No Operation
Continue the Burst
H
X
Device Deselect
Continue the Burst
SDRAM CURRENT STATE TRUTH TABLE
Current State
Command
Action
Notes
SDCE
SDRAS
SDCAS
SDWE
(BA)
SDA10-A0
Description
A11
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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