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參數(shù)資料
| 型號： | EDI9LC644V |
| 英文描述： | 128Kx32 SSRAM/1Mx32 SDRAM Array(3.3V,128x32同步靜態(tài)RAM和1Mx32同步動態(tài)RAM陣列) |
| 中文描述： | 128Kx32 SSRAM/1Mx32內(nèi)存陣列（3.3伏，128x32同步靜態(tài)內(nèi)存和1Mx32同步動態(tài)內(nèi)存陣列） |
| 文件頁數(shù)： | 16/26頁 |
| 文件大?。?/td> | 460K |
| 代理商： | EDI9LC644V |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI9LC644V
EDI9LC644AV
FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
CBc
CAd
RBb
CAa
RAa
CL = 2
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
DON'T CARE
CAb
Note 2
RBb
RAc
CL = 3
DQ
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
SDRAS
SDCAS
ADDR
A11 (BA)
BWE
SDA10
SDCLK
SDCE
SDWE
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle,
so in the case of BRSW write command, the next cycle starts the precharge.
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相關代理商/技術參數(shù) |
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| EDI9LC644V1310BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1312BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1510BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1512BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
| EDI9LC644V1610BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128Kx32 SSRAM/1Mx32 SDRAM |
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