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參數(shù)資料
| 型號： | EDE5116AJBG |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 512M比特DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 9/77頁 |
| 文件大?。?/td> | 589K |
| 代理商： | EDE5116AJBG |
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EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
9
×
8
×
16
Parameter
Symbol
Grade
max.
max.
Unit
Test condition
Auto-refresh current IDD5
-8E
-6E
105
100
105
100
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD)
interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CK and /CK at 0V; CKE
≤
0.2V;
Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD),
AL = tRCD (IDD)
1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD(IDD), tRCD = 1
×
tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during
DESELECTs; Data pattern is same as IDD4W
Self-refresh current
IDD6*
7
6
6
mA
Operating current
(Bank interleaving)
IDD7
-8E
-6E
160
150
240
230
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
7. When TC
≥
+85
°
C, IDD6 must be derated by 80%.
IDD6 will increase by this amount if TC
≥
+85
°
C and double refresh option is still enabled.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
DDR2-667
Parameter
5-5-5
5-5-5
Unit
CL (IDD)
5
5
tCK
tRCD (IDD)
12.5
15
ns
tRC (IDD)
57.5
60
ns
tRRD (IDD)-
×
8
7.5
7.5
ns
tRRD (IDD)-
×
16
10
10
ns
tCK (IDD)
2.5
3
ns
tRAS (min.)(IDD)
45
45
ns
tRAS (max.)(IDD)
70000
70000
ns
tRP (IDD)
12.5
15
ns
tRFC (IDD)
105
105
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| EDE5116AJBG-1J | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116AJBG-1J-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116AJBG-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116AJBG-6ELI-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM WTR (Wide Temperature Range) |
| EDE5116AJBG-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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