參數(shù)資料
型號(hào)： EDE5116AJBG
廠商： Elpida Memory, Inc.
英文描述： 512M bits DDR2 SDRAM
中文描述： 512M比特DDR2 SDRAM內(nèi)存
文件頁(yè)數(shù)： 38/77頁(yè)
文件大小： 589K
代理商： EDE5116AJBG
EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
38
DDR2 SDRAM Extended Mode Registers Set [EMRS]
EMRS (1) Programming
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver strength, additive
latency, ODT, /DQS disable, OCD program, RDQS enable. The default value of the extended mode register (1) is
not defined, therefore the extended mode register (1) must be written after power-up for proper operation. The
extended mode register (1) is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while
controlling the states of address pins A0 to A13. The DDR2 SDRAM should be in all banks precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command cycle time (tMRD)
must be satisfied to complete the write operation to the extended mode register (1). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3
to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is used for /DQS disable and A11 is
used for RDQS enable. A2 and A6 are used for ODT setting.
Notes: 1. A13 is reserved for future use, and must be programmed to 0 when setting the extended mode register.
2 When adjust mode is issued, AL from previously set value must be applied.
3. After setting to default, OCD mode needs to be exited by setting A9 to A7 to 000.
Refer to the chapter Off-Chip Driver (OCD)Impedance Adjustment for detailed information.
4. Output disabled - DQ, DQS, /DQS, RDQS, /RDQS. This feature is used in conjunction with DIMM
IDD measurements when IDDQ is not desired to be included.
EMRS (1)
A13
BA0
BA1
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address field
A11
0
1
RDQS enable
Disable
Enable
1
0
0
*
/DQS
OCD program
Rtt Additive latency Rtt D.I.C DLL
Extended mode register
A10
0
1
/DQS enable
Enable
Disable
A5
0
0
0
0
1
1
1
1
Additive latency
A4
0
0
1
1
0
0
1
1
A3
0
1
0
1
0
1
0
1
Latency
0
1
2
3
4
5
Reserved
Reserved
A0
0
1
DLL enable
Enable
Disable
BA1
0
0
1
1
MRS mode
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
A6
0
0
1
1
A2
0
1
0
1
Rtt (nominal )
ODT Disabled
75
Ω
150
Ω
50
Ω
A9
0
0
0
1
1
Driver impedance adjustment
A8
0
0
1
0
1
A7
0
1
0
0
1
OCD calibration mode exit
Drive(1)
Drive(0)
Adjust mode*
OCD Calibration default*
A1
0
1
Driver strength control
Output driver
impedance control
Normal
Weak
Driver
size
100%
60%
A11
(RDQS enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
A10
(/DQS enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
RDQS/DM
DM
DM
RDQS
RDQS
/RDQS
High-Z
High-Z
/RDQS
High-Z
DQS
DQS
DQS
DQS
DQS
/DQS
/DQS
High-Z
/DQS
High-Z
Operation
1
2
3
RDQS
Qoff
BA0
0
1
0
1
A12
0
1
Qoff*
Output buffers enabled
Output buffers disabled
Strobe function matrix
4
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