參數(shù)資料
型號(hào)： EDE5116AJBG
廠商： Elpida Memory, Inc.
英文描述： 512M bits DDR2 SDRAM
中文描述： 512M比特DDR2 SDRAM內(nèi)存
文件頁(yè)數(shù)： 37/77頁(yè)
文件大?。?/td> 589K
代理商： EDE5116AJBG
EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
37
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, /CAS latency, DLL reset function, write recovery time (tWR)
are user defined variables and must be programmed with a mode register set command [MRS]. Additionally, DLL
disable function, driver impedance, additive /CAS latency, ODT (On Die Termination), single-ended strobe, and OCD
(Off-Chip Driver Impedance Adjustment) are also user defined variables and must be programmed with an extended
mode register set command [EMRS]. Contents of the Mode Register (MR) or Extended Mode Registers (EMR (#))
can be altered by reexecuting the MRS and EMRS commands. If the user chooses to modify only a subset of the
MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be
executed any time after power-up without affecting array contents.
DDR2 SDRAM Mode Register Set [MRS]
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls /CAS
latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2
SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode
register must be written after power-up for proper operation. The mode register is written by asserting low on /CS,
/RAS, /CAS, /WE, BA0 and BA1, while controlling the state of address pins A0 to A13.
The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register.
The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register.
The mode register contents can be changed using the same command and clock cycle requirements during normal
operation as long as all banks are in the precharge state. The mode register is divided into various fields depending
on functionality. Burst length is defined by A0 to A2 with options of 4 and 8 bit burst lengths. The burst length
decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, /CAS latency is defined
by A4 to A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset.
A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 to A11. Refer to the
table for specific codes.
Notes: 1. BA1 and A13 are reserved for future use and must be programmed to 0 when setting the mode register.
2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.).
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer
(WR [cycles] = tWR (ns) / tCK (ns)).
The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
0
PD
BA0 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address field
0
*
1
0
*
1
BA1
WR
A8
0
1
DLL reset
No
Yes
DLL TM
/CAS latency
BT
Burst length
Mode register
A7
0
1
Mode
Normal
Test
A6
0
0
0
0
1
1
1
1
/CAS latency
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
Reserved
3
4
5
6
Reserved
A3
0
1
Burst type
Sequential
Interleave
A12
0
1
Active power down exit timing
Fast exit (use tXARD timing)
Slow exit (use tXARDS timing)
A2
0
0
Burst length
A1
1
1
A0
0
1
BL
4
8
A11
0
0
0
0
1
1
1
1
Write recovery for autoprecharge
A10
0
0
1
1
0
0
1
1
A9
0
1
0
1
0
1
0
1
WR
Reserved
2
3
4
5
6
Reserved
Reserved
BA1
0
0
1
1
MRS mode
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
BA0
0
1
0
1
D
D
D
D
Mode Register Set (MRS)
相關(guān)PDF資料
PDF描述
EDE5116AJBG-6E-E 512M bits DDR2 SDRAM
EDE5116AJBG-8E-E 512M bits DDR2 SDRAM
EDE702 Serial LCD Interface IC
EDI8808CB HIGH SPEED, LOW POWER 64K MONOLITHIC SRAM
EDI8F32256C HIGH SPEED EIGHT MEGABIT SRAM MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE5116AJBG-1J 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJBG-1J-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJBG-6E-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJBG-6ELI-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512M bits DDR2 SDRAM WTR (Wide Temperature Range)
EDE5116AJBG-8E-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:512M bits DDR2 SDRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*