參數(shù)資料
型號: EDE5116AJBG
廠商: Elpida Memory, Inc.
英文描述: 512M bits DDR2 SDRAM
中文描述: 512M比特DDR2 SDRAM內(nèi)存
文件頁數(shù): 27/77頁
文件大?。?/td> 589K
代理商: EDE5116AJBG
EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
27
Command Operation
Command Truth Table
The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Symbol
Previou
s cycle
Current
cycle
/CS
/RAS
/CAS
/WE
BA0
BA1
A13 to
A11
A10
A0 to
A9
Notes
Mode register set
Extended mode
register set (1)
Extended mode
register set (2)
Auto-refresh
MRS
H
H
L
L
L
L
L
L
MRS OPCODE
1
EMRS
H
H
L
L
L
L
H
L
EMRS (1) OPCODE
1
EMRS
H
H
L
L
L
L
L
H
EMRS (2) OPCODE
1
REF
H
H
L
L
L
H
×
×
×
×
×
1
Self-refresh entry
SELF
H
L
L
L
L
H
×
×
×
×
×
1
Self-refresh exit
SELFX L
H
H
×
×
×
×
×
×
×
×
1, 6
L
H
L
H
H
H
×
×
×
×
×
Single bank precharge
PRE
H
H
L
L
H
L
BA
×
L
×
1, 2
Precharge all banks
PALL
H
H
L
L
H
L
×
×
×
H
×
1
Bank activate
ACT
H
H
L
L
H
H
BA
RA
1, 2
Write
WRIT
H
H
L
H
L
L
BA
CA
L
CA
1, 2, 3
Write with auto precharge
WRITA H
H
L
H
L
L
BA
CA
H
CA
1, 2, 3
Read
READ
H
H
L
H
L
H
BA
CA
L
CA
1, 2, 3
Read with auto precharge
READA H
H
L
H
L
H
BA
CA
H
CA
1, 2, 3
No operation
NOP
H
×
L
H
H
H
×
×
×
×
×
1
Device deselect
DESL
H
×
H
×
×
×
×
×
×
×
×
1
Power-down mode entry
PDEN
H
L
H
×
×
×
×
×
×
×
×
1, 4
H
L
L
H
H
H
×
×
×
×
×
Power-down mode exit
PDEX
L
H
H
×
×
×
×
×
×
×
×
1, 4
Remark: H = VIH. L = VIL.
×
= VIH or VIL. BA = Bank Address, RA = Row Address, CA = Column Address
Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock.
2. Bank select (BA0, BA1), determine which bank is to be operated upon.
3. Burst reads or writes should not be terminated other than specified as
Reads interrupted by a Read
in
burst read command [READ] or
Writes interrupted by a Write
in burst write command [WRIT].
4. The power-down mode does not perform any refresh operations. The duration of power-down is therefore
limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. Self-refresh exit is asynchronous.
L
H
L
H
H
H
×
×
×
×
×
相關(guān)PDF資料
PDF描述
EDE5116AJBG-6E-E 512M bits DDR2 SDRAM
EDE5116AJBG-8E-E 512M bits DDR2 SDRAM
EDE702 Serial LCD Interface IC
EDI8808CB HIGH SPEED, LOW POWER 64K MONOLITHIC SRAM
EDI8F32256C HIGH SPEED EIGHT MEGABIT SRAM MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE5116AJBG-1J 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJBG-1J-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJBG-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5116AJBG-6ELI-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM WTR (Wide Temperature Range)
EDE5116AJBG-8E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM