參數(shù)資料
型號(hào)： EDD1216AATA-6B-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 128M bits DDR SDRAM (8M words x 16 bits)
中文描述： 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 33/49頁(yè)
文件大?。?/td> 569K
代理商： EDD1216AATA-6B-E
EDD1216AATA
Data Sheet E0444E40 (Ver. 4.0)
33
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
address
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
1
Row address State
Operation
1. Same
Same
ACTIVE
2. Same
Different
—
3. Different
Any
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
1
IDLE
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
in0
in1
in2
out0 out1
out2 out3
CK
/CK
DM
DQ
Command
t1
t0
t2
t3
t4
t5
t6
t7
t8
BL = 4
CL= 2
DQS
CL=2
Data masked
1 cycle
READ
NOP
WRIT
High-Z
High-Z
[WRITE to READ delay = 1 clock cycle]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD1216AATA-7A-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA-7B-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AJBG 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1216AJBG-5B-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1216AJBG-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
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