- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384277 > EDD1216AATA-6B-E (ELPIDA MEMORY INC) 128M bits DDR SDRAM (8M words x 16 bits) PDF資料下載
參數(shù)資料
| 型號： | EDD1216AATA-6B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 128M bits DDR SDRAM (8M words x 16 bits) |
| 中文描述： | 8M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 14/49頁 |
| 文件大小： | 569K |
| 代理商： | EDD1216AATA-6B-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
EDD1216AATA
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX11).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
Data Sheet E0444E40 (Ver. 4.0)
14
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins (the A0 to the A11, BA0 to BA1) in the mode
register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
CKE
Current state
Command
n – 1
n
/CS
/RAS
/CAS
/WE
Address
Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
2
Idle
Power down entry (PDEN)
H
L
L
H
H
H
×
H
L
H
×
×
×
×
Self refresh
Self refresh exit (SELFX)
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Power down
Power down exit (PDEX)
L
H
L
H
H
H
×
Remark: H: VIH. L: VIL.
×
: VIH or VIL.
Notes: 1. All the banks must be in IDLE before executing this command.
2. The CKE level must be kept for 1 CK cycle at least.
L
H
H
×
×
×
×
相關PDF資料 |
PDF描述 |
|---|---|
| EDD1216AASE-6B-E | ER 3C 3#8 SKT PLUG LINE |
| EDD1216AASE-7A-E | 128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AASE | 128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA | 128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA-5 | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDD1216AATA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AJBG | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1216AJBG-5B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1216AJBG-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。