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參數(shù)資料
| 型號(hào)： | EDD1216AATA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 128M bits DDR SDRAM (8M words x 16 bits) |
| 中文描述： | 128兆位DDR SDRAM內(nèi)存（800萬字× 16位） |
| 文件頁數(shù)： | 1/49頁 |
| 文件大?。?/td> | 569K |
| 代理商： | EDD1216AATA |
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Document No. E0444E40 (Ver. 4.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005
DATA SHEET
128M bits DDR SDRAM
EDD1216AATA (8M words
×
16 bits)
Description
The EDD1216AATA is a 128M bits Double Data Rate
(DDR) SDRAM organized as 2,097,154 words
×
16 bits
×
4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 66-pin plastic
TSOP (II).
Features
Power supply : VDD ,VDDQ = 2.
5
V
±
0.
2
V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles: 4096 refresh cycles/64ms
15.6
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
RoHS compliant
Pin Configurations
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
(Top view)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A11
BA0, BA1
DQ0 to DQ15
UDQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
66-pin Plastic TSOP(II)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD1216AATA-5 | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5B-E | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5C-E | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-7A-E | 128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA-7B-E | 128M bits DDR SDRAM (8M words x 16 bits) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD1216AATA-5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits) |
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