tGZ
參數(shù)資料
型號(hào): DSPB56366AG120
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 62/110頁(yè)
文件大?。?/td> 0K
描述: IC DSP 24BIT AUD 120MHZ 144-LQFP
產(chǎn)品變化通告: Product Discontinuation 24/Feb/2012
標(biāo)準(zhǔn)包裝: 60
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時(shí)鐘速率: 120MHz
非易失內(nèi)存: ROM(240 kB)
芯片上RAM: 69kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 110°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor
3-29
193 RD deassertion to data not valid4
tGZ
0.0
0.0
ns
194 WR assertion to data active
0.75
× T
C 0.3
11.1
9.1
ns
195 WR deassertion to data high impedance
0.25
× T
C
—3.8
—3.1
ns
1 The number of wait states for out-of-page access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF and not tGZ.
4 The asynchronous delays specified in the expressions are valid for DSP56366.
5 Either t
RCH or tRRH must be satisfied for read cycles.
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
No.
Characteristics3
Symbol
Expression4
Min
Max
Unit
157
Random read or write cycle time
tRC
12
× T
C
120.0
ns
158
RAS assertion to data valid (read)
tRAC
6.25
× T
C 7.0
55.5
ns
159
CAS assertion to data valid (read)
tCAC
3.75
× T
C 7.0
30.5
ns
160
Column address valid to data valid (read)
tAA
4.5
× T
C 7.0
38.0
ns
161
CAS deassertion to data not valid (read hold time)
tOFF
0.0
ns
162
RAS deassertion to RAS assertion
tRP
4.25
× T
C 4.0
38.5
ns
163
RAS assertion pulse width
tRAS
7.75
× T
C 4.0
73.5
ns
164
CAS assertion to RAS deassertion
tRSH
5.25
× T
C 4.0
48.5
ns
165
RAS assertion to CAS deassertion
tCSH
6.25
× T
C 4.0
58.5
ns
166
CAS assertion pulse width
tCAS
3.75
× T
C 4.0
33.5
ns
167
RAS assertion to CAS assertion
tRCD
2.5
× T
C ± 4.0
21.0
29.0
ns
168
RAS assertion to column address valid
tRAD
1.75
× T
C ± 4.0
13.5
21.5
ns
169
CAS deassertion to RAS assertion
tCRP
5.75
× T
C 4.0
53.5
ns
170
CAS deassertion pulse width
tCP
4.25
× T
C 4.0
38.5
ns
171
Row address valid to RAS assertion
tASR
4.25
× T
C 4.0
38.5
ns
172
RAS assertion to row address not valid
tRAH
1.75
× T
C 4.0
13.5
ns
173
Column address valid to CAS assertion
tASC
0.75
× T
C 4.0
3.5
ns
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued)
No.
Characteristics3
Symbol
Expression4
66 MHz
80 MHz
Unit
Min
Max
Min
Max
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