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參數(shù)資料
| 型號(hào)： | DSP56F827FG80E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 45/60頁 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR 16BIT 128-LQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 系列： | 56F8xx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 80MHz |
| 連通性： | EBI/EMI，SCI，SPI，SSI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲(chǔ)器容量： | 136KB（68K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 5K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.25 V ~ 2.75 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 128-LQFP |
| 包裝： | 托盤 |
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56F827 Description
56F827 Technical Data, Rev. 12
Freescale Semiconductor
5
One Synchronous Serial Interface with 6 pins (or 6 additional GPIO pins)
One 8-channel Programmable Chip Select
Sixteen dedicated and forty eight multiplexed GPIO pins (64 total)
Computer-Operating Properly (COP) Watchdog timer
Two external interrupt pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the core clock
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
One Time of Day (TOD) Timer
1.1.4
Power Information
Dual power supply, 3.3V and 2.5V
Wait and Multiple Stop modes available
1.2 56F827 Description
The 56F827 is a member of the 56800 core-based family of controllers. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F827 is well-suited for many applications.
The 56F827 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F827 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external
dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
This controller also provides a full set of standard programmable peripherals that include one 10-input,
12-bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral
Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with
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