
56F827 Technical Data, Rev. 12
44
Freescale Semiconductor
Delay from STCK high to STFS (wl) low - Master5
tTFSWLM
-1.0
—
-0.1
ns
Delay from SRCK high to SRFS (bl) low - Master5
tRFSBLM
-0.1
—
0
ns
Delay from SRCK high to SRFS (wl) low - Master5
tRFSWLM
-0.1
—
0
ns
STCK high to STXD enable from high impedance - Master
tTXEM
20
—
22
ns
STCK high to STXD valid - Master
tTXVM
24
—
26
ns
STCK high to STXD not valid - Master
tTXNVM
0.1
—
0.2
ns
STCK high to STXD high impedance - Master
tTXHIM
24
—
25.5
ns
SRXD Setup time before SRCK low - Master
tSM
4—
—
ns
SRXD Hold time after SRCK low - Master
tHM
4—
—
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master
tTSM
4—
—
SRXD Hold time after STCK low - Master
tTHM
4—
—
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
Table 3-14 SSI Master Mode1 Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Parameter
Symbol
Min
Typ
Max
Units