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參數(shù)資料
| 型號： | DS21Q55DK |
| 英文描述： | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| 中文描述： | 四路T1/E1/J1收發(fā)器開發(fā)板子卡 |
| 文件頁數(shù)： | 72/99頁 |
| 文件大小： | 325K |
| 代理商： | DS21Q55DK |
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DS21Q50
Page 72 of 99
19.3 JITTER ATTENUATORS
The DS21Q50 contains an onboard clock and data jitter attenuator for each transceiver and a single,
undedicated “clock only” jitter attenuator. This undedicated jitter attenuator is shown in the block diagram of
Figure 4-1 as the Alternate Jitter Atteunator.
19.3.1 CLOCK AND DATA JITTER ATTENUATORS
The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer
depths of either 32 or 128 bits via the Line Interface Control Register (LICR). The 128–bit mode is used in
applications where large excursions of wander are expected. The 32–bit mode is used in delay sensitive
applications. The characteristics of the attenuators are shown in Figure 19-5. The jitter attenuators can be placed
in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also,
the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order for the jitter
attenuator to operate properly, a 2.048 MHz clock ( 50 ppm) must be applied at the MCLK pin. Onboard
circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the
TCLKI pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is
acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit
side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits),
then the DS21Q50 will divide the internal nominal 32.768 MHz clock by either 15 or 17 instead of the normal 16
to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator
Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
19.3.2 UNDEDICATED CLOCK JITTER ATTENUATOR
The undedicated jitter attenuator is useful for preparing a user supplied clock for use as a transmission clock
(TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL
or other synthesizers may contain too much jitter to be appropriate for transmission. Network requirements limit
the amount of jitter that may be transmitted onto the network. The undedicated attenuator may be hardware
configured by the user.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
| DS21S07AS | Terminator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q55N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad T1/E1/J1 Transceiver |
| DS21Q58 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Quad Transceiver |
| DS21Q58L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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