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參數資料
| 型號： | DS21Q55DK |
| 英文描述： | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| 中文描述： | 四路T1/E1/J1收發(fā)器開發(fā)板子卡 |
| 文件頁數： | 52/99頁 |
| 文件大?。?/td> | 325K |
| 代理商： | DS21Q55DK |
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DS21Q50
Page 52 of 99
Table 11-2 RECEIVE PRBS MODE SELECT
RPRBS1
(CCR5.1)
(CCR5.0)
0
0
RPBRS0
MODE
Mode 0
: Normal (PRBS disabled)
Mode 1
: PRBS in TSx. PRBS pattern is received in a single time slot (TS).
In this mode the Receive Channel Monitor select bits in register CCR4 are
used to select a time slot in which to receive the PRBS pattern.
Mode 2
: PRBS in all but TS0. PRBS pattern is received in time slots 1
through 31
Mode 3
: PRBS unframed. PRBS pattern is received in all time slots
0
1
1
0
1
1
12. SYSTEM CLOCK INTERFACE
A single System Clock Interface (SCI) is common to all four transceivers on the DS21Q50. The SCI is
designed to allow any one of the four receivers to act as the master reference clock for the system. When
multiple DS21Q50s are used to build an N port system, the SCI will allow any one of the N ports to be the
master. The selected reference is then distributed to the other DS21Q50s via the REFCLK pin. The REFCLK
pin acts as an output on the DS21Q50, which has been selected to provide the reference clock from one of its
four receivers. On DS21Q50s not selected to source the reference clock, this pin becomes an input. The
reference clock is also passed to the clock synthesizer PLL to generate a 2.048MHz, 4.096MHz, 8.192MHz or
16.384MHz clock. This clock can then be used with the IBO function in order to merge up to 8 E1 lines on to a
single high-speed PCM bus. In the event that the master E1 port fails (enters a Receive Carrier Loss condition)
that port will automatically switch to the clock present on the MCLK pin. Therefore, MCLK acts as the backup
source of master clock. The host can then find and select a functioning E1 port as the master. Because the
selected port’s clock is passed to the other DS21Q50s in a multiple device configuration, one DS21Q50’s
synthesizer can always be the source of the high-speed clock. This allows smooth transitions when clock source
switching occurs. The System Clock Interface Control register exists in transceiver #1 only. (TS0, TS1 = 0)
相關PDF資料 |
PDF描述 |
|---|---|
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
| DS21S07AS | Terminator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS21Q55N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad T1/E1/J1 Transceiver |
| DS21Q58 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Quad Transceiver |
| DS21Q58L | 功能描述:網絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58L+ | 功能描述:網絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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