- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376965 > DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit Daughter Card PDF資料下載
參數(shù)資料
| 型號(hào)： | DS21Q55DK |
| 英文描述： | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| 中文描述： | 四路T1/E1/J1收發(fā)器開發(fā)板子卡 |
| 文件頁(yè)數(shù)： | 28/99頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | DS21Q55DK |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)
DS21Q50
Page 28 of 99
Register Name:
Register Description:
Register Address:
Bit #
SYM
SYMBOL
IFSS
TCR
TRANSMIT CONTROL REGISTER
11 Hex
7
6
5
4
3
2
1
0
IFSS
TFPT
AEBE
TUA1
TSiS
TSA1
TSM
TSIO
BIT NAME AND DESCRIPTION
7
Internal Frame Sync Select.
0 = TSYSC normal
1 = If TSYNC is in the INPUT mode (TSIO = 0) then TSYNC is
internally replaced by the recovered receive frame sync. The TSYNC
pin is ignored
1 = If TSYNC is in the OUTPUT mode (TSIO = 1) then TSYNC
outputs the recovered multiframe frame sync.
6
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF
and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
5
Automatic E–Bit Enable.
0 = E–bits not automatically set in the transmit direction
1 = E–bits automatically set in the transmit direction
4
Transmit Unframed All Ones.
0 = transmit data normally
1 = transmit an unframed all one’s code
3
Transmit International Bit Select.
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, TCR.6
must be set to 0)
2
Transmit Signaling All Ones.
0 = normal operation
1 = force timeslot 16 in every frame to all ones
1
TSYNC Mode Select.
0 = frame mode (see the timing in Section 22.2)
1 = CAS and CRC4 multiframe mode (see the timing in Section 22.2)
0
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
TFPT
Transmit Timeslot 0 Pass Through.
AEBE
TUA1
TSiS
TSA1
TSM
TSIO
NOTE: See Figure 22-9 for more details about how the Transmit Control Register affects the operation of the
DS21Q50.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
| DS21S07AS | Terminator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q55N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad T1/E1/J1 Transceiver |
| DS21Q58 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Quad Transceiver |
| DS21Q58L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。