參數(shù)資料
型號: DS21Q55DK
英文描述: Quad T1/E1/J1 Transceiver Design Kit Daughter Card
中文描述: 四路T1/E1/J1收發(fā)器開發(fā)板子卡
文件頁數(shù): 56/99頁
文件大?。?/td> 325K
代理商: DS21Q55DK
DS21Q50
Page 56 of 99
14. IDLE CODE INSERTION
The Transmit Idle Registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the
code placed in the Transmit Idle Definition Register (TIDR). This allows the same 8–bit code to be placed into
any of the 32 E1 channels.
Each of the bit positions in the Transmit Idle Registers represents a DS0 channel in the outgoing frame. When
these bits are set to a one, the corresponding channel will transmit the Idle Code contained in the Transmit Idle
Definition Register (TIDR).
Register Name:
TIR1, TIR2, TIR3, TIR4
Register Description:
TRANSMIT IDLE REGISTERS
Register Address:
24 Hex, 25 Hex, 26 Hex, 27 Hex
Bit #
7
6
5
4
3
SYM
CH8
CH7
CH6
CH5
CH4
SYM
CH16
CH15
CH14
CH13
CH12
SYM
CH24
CH23
CH22
CH21
CH20
SYM
CH32
CH31
CH30
CH29
CH28
SYMBOLS
BIT
NAME AND DESCRIPTION
CH1 - CH32 TIR1.0 - 4.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
Register Name:
TIDR
Register Description:
TRANSMIT IDLE DEFINITION REGISTER
Register Address:
23 Hex
Bit #
7
6
5
4
SYM
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
SYMBOL
BIT
NAME AND DESCRIPTION
TIDR7
7
MSB of the Idle Code (this bit is transmitted first)
TIDR6
6
TIDR5
5
TIDR4
4
TIDR3
3
TIDR2
2
TIDR1
1
TIDR0
0
LSB of the Idle Code (this bit is transmitted last)
2
1
0
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
CH9
CH17
CH25
3
2
1
0
TIDR2
TIDR1
TIDR0
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