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參數(shù)資料
| 型號： | DS21Q55DK |
| 英文描述： | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| 中文描述： | 四路T1/E1/J1收發(fā)器開發(fā)板子卡 |
| 文件頁數(shù)： | 35/99頁 |
| 文件大小： | 325K |
| 代理商： | DS21Q55DK |
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DS21Q50
Page 35 of 99
8. STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of a framer in the DS21Q50,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer status
Register (SSR).
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be
set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The Synchronizer
Status Register contents are not latched. This means that if an event or an alarm occurs and a bit is set to a one in
any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will
not be set again until the event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms,
the bit will remain set if the alarm is still present).
The user will always precede a read of the SR1, SR2 and RIR registers with a write. The byte written to the
register will inform the framer which bits the user wishes to read and have cleared. The user will write a byte to
one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or
she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will
be updated with the latest information. When a zero is written to a bit position, the read register will not be
updated and the previous value will be held. A write to the status and information registers will be immediately
followed by a read of the same register. The read result should be logically AND’ed with the mask byte that was
just written and this value should be written back into the same register to insure that bit does indeed clear. This
second write step is necessary because the alarms and events in the status registers occur asynchronously in
respect to their access via the parallel port. This write–read– write scheme allows an external microcontroller or
microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is
key in controlling the DS21Q50 with higher–order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status of the
synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with
a write.
The SR1and SR2 registers have the unique ability to initiate a hardware interrupt via the INT* output pin. Each of
the alarms and events in SR1and SR2 can be either masked or unmasked from the interrupt pin via Interrupt
Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2).
The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the
interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF,
LOTC, RCMF, and TSLIP). The alarm caused interrupts will force the INT* pin low whenever the alarm
changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 8-1). The INT*
pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused
the interrupt to occur even if the alarm is still present.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be allowed to
return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
相關PDF資料 |
PDF描述 |
|---|---|
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
| DS21S07AS | Terminator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q55N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad T1/E1/J1 Transceiver |
| DS21Q58 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Quad Transceiver |
| DS21Q58L | 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58L+ | 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q58LN | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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