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| 型號(hào)： | DS21448LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 25/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU QUAD E1/T1/J1 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 管件 |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
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6.2 Loopbacks
6.2.1 Remote Loopback (RLB)
When RLB (CCR6.6) is enabled, the DS21448 is placed into remote loopback. In this loopback, data from the
clock/data recovery state machine is looped back to the transmit path, passing through the jitter attenuator if it is
enabled. The data at the RPOS and RNEG pins is valid, while data presented at TPOS and TNEG is ignored. See
Figure 1-1 for more details.
If the automatic RLB enable (CCR6.5) is set to 1, the DS21448 automatically goes into remote loopback when it
detects the loop-up code programmed in the receive-up code definition registers (RUPCD1 and RUPCD2) for a
minimum of 5 seconds. When the DS21448 detects the loop-down code programmed in the receive loop-down
code definition registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds, the DS21448 comes out of remote
loopback. Setting ARLBE to 0 can also disable the ARLB.
6.2.2 Local Loopback (LLB)
When LLB (CCR6.7) is set to 1, the DS21448 is placed into local loopback. In this loopback, data on the transmit
side is transmitted as normal. TCLK and TPOS/TNEG pass through the jitter attenuator (if enabled) and are output
at RCLK and RPOS/RNEG. Incoming data from the line at RTIP and RRING is ignored. If transmit unframed all
ones (CCR3.7) is set to 1 while in LLB, TTIP and TRING transmit all ones while TCLK and TPOS/TNEG are looped
back to RCLK and RPOS/RNEG. See Figure 1-1 for more details.
6.2.3 Analog Loopback (LLB)
Setting ALB (CCR6.4) to 1 puts the DS21448 in analog loopback. Signals at TTIP and TRING are internally
connected to RTIP and RRING. The incoming signals at RTIP and RRING are ignored. The signals at TTIP and
TRING are transmitted as normal. See Figure 1-1 for more details.
6.2.4 Dual Loopback (DLB)
Setting CCR6.7 and CCR6.6 (LLB and RLB, respectively) to 1 puts the DS21448 into dual loopback operation. The
TCLK and TPOS/TNEG signals are looped back through the jitter attenuator (if enabled) and output at RCLK and
RPOS/RNEG. Clock and data recovered from RTIP and RRING are looped back to the transmit side and output at
TTIP and TRING. This mode of operation is not available when implementing hardware operation. See Figure 1-1
more details.
6.3 PRBS Generation and Detection
Setting TPRBSE (CCR3.4) = 1 enables the DS21448 to transmit a 2
15 - 1 (E1) or a QRSS (T1) PRBS, depending
on the ETS bit setting in CCR1.7. The DS21448’s receive side always searches for these PRBS patterns
independently of CCR3.4. The PRBS bit-error output (PBEO) remains high until the receiver has synchronized to
one of the two patterns (64 bits received without an error), at which time PBEO goes low, and the PRBSD bit in the
SR is set. Once synchronized, any bit errors received cause a positive-going pulse at PBEO, synchronous with
RCLK. This output can be used with external circuitry track bit-error rates during the PRBS testing. Setting CCR6.2
(ECRS2) = 1 allows the PRBS errors to be accumulated in the 16-bit counter in registers ECR1 and ECR2. The
PRBS synchronizer remains in sync until it experiences six bit errors or more within a 64-bit span. Both PRBS
patterns comply with the ITU-T O.151 specifications.
6.4 Error Counter
Error count register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a user-
selectable 16-bit counter that records incoming errors, including BPVs, code violations (CVs), excessive zero
violations (EXZs), and/or PRBS errors. See Table 6-C, Table 6-D, and Figure 1-2 for details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21448LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448-LW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2145 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| DS21455 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1-T1-J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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