參數(shù)資料
型號(hào): DS21448LN+
廠商: Maxim Integrated Products
文件頁數(shù): 10/60頁
文件大小: 0K
描述: IC LIU QUAD E1/T1/J1 128-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: T1/E1/J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21448 3.3V T1/E1/J1 Quad Line Interface
18 of 60
4.3 Parallel Port Operation
The option for either multiplexed bus operation (BIS0 = 0) or nonmultiplexed bus operation (BIS0 = 1) is available
when using the parallel interface. The DS21448 can operate with either Intel or Motorola bus timing configurations.
If the PBTS pin is wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus
signals are listed in parentheses (). Four sets of identical register maps exist, one for each channel. See Table 4-H
for register names and addresses. Use the appropriate chip select (
CS1, CS2, CS3, or CS4) to access a channel’s
register map. See the timing diagrams in Section 10 for more details. Hardware and serial port modes are not
supported when using parallel port operation.
4.3.1 Device Power-Up and Reset
The DS21448 resets itself upon power-up, setting all writeable registers to 00h and clearing the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the power
supplies have settled, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2). The
DS21448 can at any time be reset to the default settings by bringing
HRST low (level triggered) or by powering
down and powering up again.
Table 4-G. Parallel Port Mode Selection
PBTS
BIS0
PROCESSOR
BUS INTERFACE TYPE
0
Intel
Parallel Port Mode (Multiplexed)
0
1
Intel
Parallel Port Mode (Nonmultiplexed)
1
0
Motorola
Parallel Port Mode (Multiplexed)
1
Motorola
Parallel Port Mode (Nonmultiplexed)
4.3.2 Register Map
Table 4-H shows the typical register map for all four ports. Use the appropriate chip select (
CS1, CS2, CS3, or CS4)
to access a channel’s register map.
Table 4-H. Register Map
NAME
R/W
ADDRESS
FUNCTION
CCR1
R/W
00h
Common Control Register 1
CCR2
R/W
01h
Common Control Register 2
CCR3
R/W
02h
Common Control Register 3
CCR4
R/W
03h
Common Control Register 4
CCR5
R/W
04h
Common Control Register 5
CCR6
R/W
05h
Common Control Register 6
SR
R
06h
Status Register
IMR
R/W
07h
Interrupt Mask Register
RIR1
R
08h
Receive Information Register 1
RIR2
R
09h
Receive Information Register 2
IBCC
R/W
0Ah
In-Band Code Control Register
TCD1
R/W
0Bh
Transmit Code Definition Register 1
TCD2
R/W
0Ch
Transmit Code Definition Register 2
RUPCD1
R/W
0Dh
Receive-Up Code Definition Register 1
RUPCD2
R/W
0Eh
Receive-Up Code Definition Register 2
RDNCD1
R/W
0Fh
Receive-Down Code Definition Register 1
RDNCD2
R/W
10h
Receive-Down Code Definition Register 2
ECR1
R
11h
Error Count Register 1
ECR2
R
12h
Error Count Register 2
TEST1
R/W
13h
Test 1
TEST2
R/W
14h
Test 2
TEST2
R/W
15h
Test 3
(Note 1)
Note 1: Register addresses 16h–1Fh do not exist.
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